| /openbmc/qemu/docs/system/ |
| H A D | barrier.rst | 1 QEMU Barrier Client
12 The QEMU Barrier client avoids this by implementing directly the Barrier
15 `Barrier <https://github.com/debauchee/barrier>`__
19 This protocol is enabled by adding an input-barrier object to QEMU.
23 input-barrier,id=<object-id>,name=<guest display name>
24 [,server=<barrier server address>][,port=<barrier server port>]
30 -object input-barrier,id=barrier0,name=VM-1
32 where VM-1 is the name the display configured in the Barrier server
35 by default ``<barrier server address>`` is ``localhost``,
39 If the Barrier server is stopped QEMU needs to be reconnected manually,
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| /openbmc/linux/tools/include/asm/ |
| H A D | barrier.h | 4 #include "../../arch/x86/include/asm/barrier.h"
6 #include "../../arch/arm/include/asm/barrier.h"
8 #include "../../arch/arm64/include/asm/barrier.h"
10 #include "../../arch/powerpc/include/asm/barrier.h"
12 #include "../../arch/s390/include/asm/barrier.h"
14 #include "../../arch/sh/include/asm/barrier.h"
16 #include "../../arch/sparc/include/asm/barrier.h"
18 #include "../../arch/tile/include/asm/barrier.h"
20 #include "../../arch/alpha/include/asm/barrier.h"
22 #include "../../arch/mips/include/asm/barrier.h"
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| /openbmc/linux/include/linux/ |
| H A D | spinlock_up.h | 9 #include <asm/barrier.h>
32 barrier(); in arch_spin_lock()
40 barrier(); in arch_spin_trylock()
47 barrier(); in arch_spin_unlock()
54 #define arch_read_lock(lock) do { barrier(); (void)(lock); } while (0)
55 #define arch_write_lock(lock) do { barrier(); (void)(lock); } while (0)
56 #define arch_read_trylock(lock) ({ barrier(); (void)(lock); 1; })
57 #define arch_write_trylock(lock) ({ barrier(); (void)(lock); 1; })
58 #define arch_read_unlock(lock) do { barrier(); (void)(lock); } while (0)
59 #define arch_write_unlock(lock) do { barrier(); (void)(lock); } while (0)
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | irqflags.h | 9 #include <asm/barrier.h>
32 barrier(); in __daif_local_irq_enable()
34 barrier(); in __daif_local_irq_enable()
44 barrier(); in __pmr_local_irq_enable()
47 barrier(); in __pmr_local_irq_enable()
61 barrier(); in __daif_local_irq_disable()
63 barrier(); in __daif_local_irq_disable()
73 barrier(); in __pmr_local_irq_disable()
75 barrier(); in __pmr_local_irq_disable()
181 barrier(); in __daif_local_irq_restore()
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| /openbmc/linux/Documentation/ |
| H A D | memory-barriers.txt | 29 particular barrier, and
34 for any particular barrier, but if the architecture provides less than
37 Note also that it is possible that a barrier may be a no-op for an
38 architecture because the way that arch works renders an explicit barrier
53 - Varieties of memory barrier.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
64 - Compiler barrier.
74 (*) Inter-CPU acquiring barrier effects.
85 (*) Kernel I/O barrier effects.
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| /openbmc/linux/arch/sparc/include/asm/ |
| H A D | barrier_64.h | 6 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
10 * It used to be believed that the memory barrier had to be right in the
11 * delay slot, but a case has been traced recently wherein the memory barrier
23 * the memory barrier explicitly into a "branch always, predicted taken"
44 barrier(); \
52 barrier(); \
56 #define __smp_mb__before_atomic() barrier()
57 #define __smp_mb__after_atomic() barrier()
59 #include <asm-generic/barrier.h>
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | sync.h | 11 * Two types of barrier are provided:
18 * restrictions imposed by the barrier.
31 * b) Multiple variants of ordering barrier are provided which allow the
34 * than a barrier are observed prior to stores that are younger than a
35 * barrier & don't care about the ordering of loads then the 'wmb'
36 * ordering barrier can be used. Limiting the barrier's effects to stores
49 * A full completion barrier; all memory accesses appearing prior to this sync
56 * For now we use a full completion barrier to implement all sync types, until
66 * barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform
104 * don't implicitly provide a memory barrier. In general this is most MIPS
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| /openbmc/linux/tools/virtio/ringtest/ |
| H A D | main.h | 91 /* Compiler barrier - similar to what Linux uses */
92 #define barrier() asm volatile("" ::: "memory") macro
98 #define cpu_relax() barrier()
113 barrier(); in busy_wait()
130 * adds a compiler barrier.
133 barrier(); \
139 barrier(); \
143 #define smp_wmb() barrier()
163 barrier(); in __read_once_size()
165 barrier(); in __read_once_size()
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| H A D | virtio_ring_0_9.c | 133 /* Barrier A (for pairing) */ in add_inbuf()
140 /* Barrier A (for pairing) */ in add_inbuf()
145 /* Barrier A (for pairing) */ in add_inbuf()
163 /* Barrier B (for pairing) */ in get_buf()
169 /* Barrier B (for pairing) */ in get_buf()
221 /* Barrier D (for pairing) */ in enable_call()
231 /* Barrier C (for pairing) */ in kick_available()
253 /* Barrier C (for pairing) */ in enable_kick()
280 /* Barrier A (for pairing) */ in use_buf()
289 /* Barrier A (for pairing) */ in use_buf()
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| /openbmc/linux/kernel/sched/ |
| H A D | membarrier.c | 13 * barrier before sending the IPI
19 * The memory barrier at the start of membarrier() on CPU0 is necessary in
22 * CPU1 after the IPI-induced memory barrier:
33 * barrier()
40 * point after (b). If the memory barrier at (a) is omitted, then "x = 1"
45 * The timing of the memory barrier at (a) has to ensure that it executes
46 * before the IPI-induced memory barrier on CPU1.
49 * barrier after completing the IPI
55 * The memory barrier at the end of membarrier() on CPU0 is necessary in
63 * barrier()
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | barrier.h | 51 /* Prevent speculative execution past this barrier. */
54 #define __dma_rmb() barrier()
55 #define __dma_wmb() barrier()
60 #define __smp_wmb() barrier()
66 barrier(); \
74 barrier(); \
82 /* Writing to CR3 provides a full memory barrier in switch_mm(). */
85 #include <asm-generic/barrier.h>
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| /openbmc/u-boot/include/linux/ |
| H A D | compiler-intel.h | 16 #undef barrier
21 #define barrier() __memory_barrier() macro
22 #define barrier_data(ptr) barrier()
29 /* This should act as an optimization barrier on var.
30 * Given that this compiler does not have inline assembly, a compiler barrier
33 #define OPTIMIZER_HIDE_VAR(var) barrier()
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| /openbmc/linux/arch/s390/include/asm/ |
| H A D | barrier.h | 30 #define __rmb() barrier()
31 #define __wmb() barrier()
41 barrier(); \
49 barrier(); \
53 #define __smp_mb__before_atomic() barrier()
54 #define __smp_mb__after_atomic() barrier()
80 #include <asm-generic/barrier.h>
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| /openbmc/qemu/subprojects/libvhost-user/include/ |
| H A D | atomic.h | 20 /* Compiler barrier */
21 #define barrier() ({ asm volatile("" ::: "memory"); (void)0; }) macro
29 *__atomic_thread_fence does not include a compiler barrier; instead,
30 * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
31 * semantics. If smp_wmb() is a no-op, absence of the barrier means that
32 * the compiler is free to reorder stores on each side of the barrier.
36 #define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
37 #define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
38 #define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
41 * no processors except Alpha need a barrier here. Leave it in if
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| /openbmc/qemu/subprojects/libvduse/include/ |
| H A D | atomic.h | 20 /* Compiler barrier */
21 #define barrier() ({ asm volatile("" ::: "memory"); (void)0; }) macro
29 *__atomic_thread_fence does not include a compiler barrier; instead,
30 * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
31 * semantics. If smp_wmb() is a no-op, absence of the barrier means that
32 * the compiler is free to reorder stores on each side of the barrier.
36 #define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
37 #define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
38 #define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
41 * no processors except Alpha need a barrier here. Leave it in if
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| /openbmc/qemu/include/qemu/ |
| H A D | atomic.h | 20 /* Compiler barrier */
21 #define barrier() ({ asm volatile("" ::: "memory"); (void)0; }) macro
29 *__atomic_thread_fence does not include a compiler barrier; instead,
30 * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
31 * semantics. If smp_wmb() is a no-op, absence of the barrier means that
32 * the compiler is free to reorder stores on each side of the barrier.
36 #define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
37 #define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
38 #define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
41 * no processors except Alpha need a barrier here. Leave it in if
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| /openbmc/linux/arch/arc/include/asm/ |
| H A D | barrier.h | 15 * Explicit barrier provided by DMB instruction
19 * - DMB guarantees SMP as well as local barrier semantics
20 * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
21 * UP: barrier(), SMP: smp_*mb == *mb)
23 * in the general case. Plus it only provides full barrier.
42 #include <asm-generic/barrier.h>
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| /openbmc/linux/tools/perf/tests/ |
| H A D | sigtrap.c | 124 pthread_barrier_t *barrier = (pthread_barrier_t *)arg; in test_thread() local
128 pthread_barrier_wait(barrier); in test_thread()
137 static int run_test_threads(pthread_t *threads, pthread_barrier_t *barrier) in run_test_threads() argument
141 pthread_barrier_wait(barrier); in run_test_threads()
148 static int run_stress_test(int fd, pthread_t *threads, pthread_barrier_t *barrier) in run_stress_test() argument
156 ret = run_test_threads(threads, barrier); in run_stress_test()
178 pthread_barrier_t barrier; in test__sigtrap() local
187 pthread_barrier_init(&barrier, NULL, NUM_THREADS + 1); in test__sigtrap()
210 if (pthread_create(&threads[i], NULL, test_thread, &barrier)) { in test__sigtrap()
216 ret = run_stress_test(fd, threads, &barrier); in test__sigtrap()
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| /openbmc/linux/arch/mips/mm/ |
| H A D | tlb-r3k.c | 32 #define BARRIER \ macro
49 entry++; /* BARRIER */ in local_flush_tlb_from()
94 start += PAGE_SIZE; /* BARRIER */ in local_flush_tlb_range()
99 if (idx < 0) /* BARRIER */ in local_flush_tlb_range()
131 start += PAGE_SIZE; /* BARRIER */ in local_flush_tlb_kernel_range()
136 if (idx < 0) /* BARRIER */ in local_flush_tlb_kernel_range()
164 BARRIER; in local_flush_tlb_page()
169 if (idx < 0) /* BARRIER */ in local_flush_tlb_page()
203 BARRIER; in __update_tlb()
208 if (idx < 0) { /* BARRIER */ in __update_tlb()
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| /openbmc/linux/arch/ia64/include/asm/ |
| H A D | barrier.h | 3 * Memory barrier definitions. This is based on information published
48 #define __smp_mb__before_atomic() barrier()
49 #define __smp_mb__after_atomic() barrier()
59 barrier(); \
67 barrier(); \
72 * The group barrier in front of the rsm & ssm are necessary to ensure
77 #include <asm-generic/barrier.h>
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| /openbmc/linux/tools/arch/sparc/include/asm/ |
| H A D | barrier_64.h | 8 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
12 * It used to be believed that the memory barrier had to be right in the
13 * delay slot, but a case has been traced recently wherein the memory barrier
25 * the memory barrier explicitly into a "branch always, predicted taken"
45 barrier(); \
52 barrier(); \
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| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | membarrier.h | 10 * Only need the full barrier when switching between processes. in membarrier_arch_switch_mm()
11 * Barrier when switching from kernel to userspace is not in membarrier_arch_switch_mm()
12 * required here, given that it is implied by mmdrop(). Barrier in membarrier_arch_switch_mm()
23 * The membarrier system call requires a full memory barrier in membarrier_arch_switch_mm()
25 * Matches a full barrier in the proximity of the membarrier in membarrier_arch_switch_mm()
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| /openbmc/linux/include/asm-generic/ |
| H A D | barrier.h | 3 * Generic barrier definitions.
61 #define mb() barrier()
113 #define smp_mb() barrier()
117 #define smp_rmb() barrier()
121 #define smp_wmb() barrier()
182 #define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
186 #define smp_mb__before_atomic() barrier()
190 #define smp_mb__after_atomic() barrier()
197 barrier(); \
207 barrier(); \
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| /openbmc/linux/arch/loongarch/include/asm/ |
| H A D | barrier.h | 12 * Bit3: barrier for previous read (0: true, 1: false)
13 * Bit2: barrier for previous write (0: true, 1: false)
14 * Bit1: barrier for succeeding read (0: true, 1: false)
15 * Bit0: barrier for succeeding write (0: true, 1: false)
17 * Hint 0x700: barrier for "read after read" from the same address
60 #define __smp_mb__before_atomic() barrier()
61 #define __smp_mb__after_atomic() barrier()
137 #include <asm-generic/barrier.h>
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | smp-tbsync.c | 53 barrier(); in smp_generic_take_timebase()
59 barrier(); in smp_generic_take_timebase()
70 barrier(); in smp_generic_take_timebase()
96 barrier(); in start_contest()
99 barrier(); in start_contest()
104 barrier(); in start_contest()
125 barrier(); in smp_generic_give_timebase()
166 barrier(); in smp_generic_give_timebase()
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