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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dbase.c52 /* Denies access to BAR2 when it's not initialised, used by INSTMEM in nvkm_bar_bar2_vmm()
56 if (bar && bar->bar2) in nvkm_bar_bar2_vmm()
57 return bar->func->bar2.vmm(bar); in nvkm_bar_bar2_vmm()
65 if (bar && bar->bar2) { in nvkm_bar_bar2_reset()
66 bar->func->bar2.init(bar); in nvkm_bar_bar2_reset()
67 bar->func->bar2.wait(bar); in nvkm_bar_bar2_reset()
75 if (bar && bar->bar2) { in nvkm_bar_bar2_fini()
76 bar->func->bar2.fini(bar); in nvkm_bar_bar2_fini()
77 bar->bar2 = false; in nvkm_bar_bar2_fini()
85 if (bar && bar->subdev.oneinit && !bar->bar2 && bar->func->bar2.init) { in nvkm_bar_bar2_init()
[all …]
H A Dnv50.c91 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4); in nv50_bar_bar2_init()
128 /* BAR2 */ in nv50_bar_oneinit()
136 &bar2_lock, "bar2", &bar->bar2_vmm); in nv50_bar_oneinit()
151 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2); in nv50_bar_oneinit()
155 nvkm_kmap(bar->bar2); in nv50_bar_oneinit()
156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); in nv50_bar_oneinit()
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000); in nv50_bar_oneinit()
[all …]
H A Dgf100.c103 (bar_nr == 3) ? "bar2" : "bar1", &bar_vm->vmm); in gf100_bar_oneinit_bar()
130 /* BAR2 */ in gf100_bar_oneinit()
131 if (bar->base.func->bar2.init) { in gf100_bar_oneinit()
184 .bar2.init = gf100_bar_bar2_init,
185 .bar2.fini = gf100_bar_bar2_fini,
186 .bar2.wait = gf100_bar_bar1_wait,
187 .bar2.vmm = gf100_bar_bar2_vmm,
H A Dgm107.c54 .bar2.init = gf100_bar_bar2_init,
55 .bar2.fini = gf100_bar_bar2_fini,
56 .bar2.wait = gm107_bar_bar2_wait,
57 .bar2.vmm = gf100_bar_bar2_vmm,
H A Dg84.c51 .bar2.init = nv50_bar_bar2_init,
52 .bar2.fini = nv50_bar_bar2_fini,
53 .bar2.wait = nv50_bar_bar1_wait,
54 .bar2.vmm = nv50_bar_bar2_vmm,
H A Dtu102.c87 .bar2.init = tu102_bar_bar2_init,
88 .bar2.fini = tu102_bar_bar2_fini,
89 .bar2.wait = tu102_bar_bar2_wait,
90 .bar2.vmm = gf100_bar_bar2_vmm,
/openbmc/openbmc/poky/meta/classes-recipe/
H A Dcore-image.bbclass63 # IMAGE_FEATURES_REPLACES_foo = 'bar1 bar2'
64 # Including image feature foo would replace the image features bar1 and bar2
71 # IMAGE_FEATURES_CONFLICTS_foo = 'bar1 bar2'
72 # An error exception would be raised if both image features foo and bar1(or bar2) are included
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dpci-octeon.h22 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
36 * For PCI (not PCIe) the BAR2 base address.
/openbmc/linux/Documentation/doc-guide/
H A Dparse-headers.rst160 enum foo { BAR1, BAR2, PRIVATE };
165 replace symbol BAR2 :c:type:\`foo\`
170 enum foo { BAR1, BAR2, PRIVATE };
172 It will make the BAR1 and BAR2 enum symbols to cross reference the foo
H A Dkernel-doc.rst310 /** @bar2: Description for struct @bar2 inside @foo */
313 * @bar2.barbar: Description for @barbar inside @foo.bar2
316 } bar2;
/openbmc/linux/Documentation/translations/it_IT/doc-guide/
H A Dparse-headers.rst165 enum foo { BAR1, BAR2, PRIVATE };
170 replace symbol BAR2 :c:type:\`foo\`
175 enum foo { BAR1, BAR2, PRIVATE };
177 Genererà un riferimento ai valori BAR1 e BAR2 dal simbolo foo nel dominio C.
/openbmc/linux/Documentation/translations/zh_CN/doc-guide/
H A Dparse-headers.rst153 enum foo { BAR1, BAR2, PRIVATE };
158 replace symbol BAR2 :c:type:\`foo\`
163 enum foo { BAR1, BAR2, PRIVATE };
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_hw.c742 * t4vf_bar2_sge_qregs - return BAR2 SGE Queue register information
746 * @pbar2_qoffset: BAR2 Queue Offset
747 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
749 * Returns the BAR2 SGE Queue Registers information associated with the
754 * This may return an error which indicates that BAR2 SGE Queue
758 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
759 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
761 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
763 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
776 /* T4 doesn't support BAR2 SGE Queue registers. in t4vf_bar2_sge_qregs()
[all …]
H A Dadapter.h146 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
147 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
188 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
189 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
252 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
253 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
369 void __iomem *bar2; member
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dinstmem.h16 /* <=nv4x: protects NV_PRAMIN/BAR2 MM
17 * >=nv50: protects BAR2 MM & LRU
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra234-xusb.yaml26 - description: XUSB bar2 registers
32 - const: bar2
128 reg-names = "hcd", "fpci", "bar2";
/openbmc/qemu/qapi/
H A Dcommon.json84 # @bar2: PCI BAR2 is used for the feature
95 'data': [ 'off', 'auto', 'bar0', 'bar1', 'bar2', 'bar3', 'bar4', 'bar5' ] }
/openbmc/qemu/docs/specs/
H A Dpci-testdev.rst7 The device implements up to three BARs: BAR0, BAR1 and BAR2.
36 BAR2 is a 64bit memory BAR, without backing storage. It is disabled
H A Divshmem-spec.rst33 - BAR2 maps the shared memory object
37 - If you only need the shared memory part, BAR2 suffices. This way,
46 Before QEMU 2.6.0, BAR2 can initially be invalid if the device is
51 accessing BAR2.
/openbmc/u-boot/test/py/tests/
H A Dtest_env.py279 set_var(state_test_env, 'foo2', 'bar2')
293 validate_set(state_test_env, 'foo2', 'bar2')
316 set_var(state_test_env, 'foo2', 'bar2')
330 validate_set(state_test_env, 'foo2', 'bar2')
/openbmc/linux/drivers/pci/endpoint/functions/
H A Dpci-epf-ntb.c187 * | BAR2 | | Doorbell 3 +-------+ | +-----------------+
231 * mapped to a single BAR (BAR2) above for 32-bit BARs. The exact BAR that's
333 *| BAR2 | | Doorbell 3 +---+ | |
436 *| BAR2 | | Doorbell 3 +-------+ | +-----------------+
714 *| BAR2 | Local Memory | BAR2 |
759 *| BAR2 | Local Memory | BAR2 |
830 * | BAR2 | Local Memory | BAR2 |
875 * | BAR2 | Local Memory | BAR2 |
934 * | BAR2 | Local Memory | BAR2 |
975 * | BAR2 | Local Memory | BAR2 |
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dpci.c171 * We need to re-allocate PCI BAR2 address range to the in intel_dc21285_init()
172 * PCI ROM BAR, and disable PCI BAR2. in intel_dc21285_init()
206 * We need to undo the PCI BAR2/PCI ROM BAR address alteration. in intel_dc21285_exit()
/openbmc/linux/drivers/bluetooth/
H A Dhci_bcm4377.c531 * bar1: iomem pointing to BAR2
560 void __iomem *bar2; member
833 bootstage = ioread32(bcm4377->bar2 + BCM4377_BAR2_BOOTSTAGE); in bcm4377_irq()
834 rti_status = ioread32(bcm4377->bar2 + BCM4377_BAR2_RTI_STATUS); in bcm4377_irq()
1817 bootstage = ioread32(bcm4377->bar2 + BCM4377_BAR2_BOOTSTAGE); in bcm4377_boot()
1818 rti_status = ioread32(bcm4377->bar2 + BCM4377_BAR2_RTI_STATUS); in bcm4377_boot()
1852 iowrite32(lower_32_bits(fw_dma), bcm4377->bar2 + BCM4377_BAR2_FW_LO); in bcm4377_boot()
1853 iowrite32(upper_32_bits(fw_dma), bcm4377->bar2 + BCM4377_BAR2_FW_HI); in bcm4377_boot()
1854 iowrite32(fw->size, bcm4377->bar2 + BCM4377_BAR2_FW_SIZE); in bcm4377_boot()
1911 iowrite32(0, bcm4377->bar2 + BCM4377_BAR2_RTI_WINDOW_LO); in bcm4377_setup_rti()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgv100.c119 const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL; in gv100_ectx_ce_bind() local
122 nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2)); in gv100_ectx_ce_bind()
123 nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2)); in gv100_ectx_ce_bind()
409 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
/openbmc/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst241 BAR2 Peer Scratchpad
263 BAR2 Doorbell + Memory Window 1
281 | BAR2 | Local Memory | BAR2 |
309 | BAR2 | | Doorbell 3 +-------+ | +-----------------+

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