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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
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/openbmc/qemu/pc-bios/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
23 serial0 = "/axi/serial@83e00000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/openbmc/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/openbmc/linux/drivers/dma/dw-axi-dmac/
H A Ddw-axi-dmac-platform.c1 // SPDX-License-Identifier: GPL-2.0
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5 * Synopsys DesignWare AXI DMA Controller driver.
15 #include <linux/dma-mapping.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include "dw-axi-dmac.h"
34 #include "../virt-dma.h"
37 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
38 * master data bus width up to 512 bits (for both AXI master interfaces), but
57 iowrite32(val, chip->regs + reg); in axi_dma_iowrite32()
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/openbmc/linux/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-tmc-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/dma-mapping.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
36 struct coresight_device *csdev = drvdata->csdev; in tmc_wait_for_tmcready()
37 struct csdev_access *csa = &csdev->access; in tmc_wait_for_tmcready()
41 dev_err(&csdev->dev, in tmc_wait_for_tmcready()
43 return -EBUSY; in tmc_wait_for_tmcready()
50 struct coresight_device *csdev = drvdata->csdev; in tmc_flush_and_stop()
51 struct csdev_access *csa = &csdev->access; in tmc_flush_and_stop()
[all …]
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
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/openbmc/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence USBHS-DEV Driver - gadget side.
28 #include <linux/dma-mapping.h>
35 #include "cdns2-gadget.h"
36 #include "cdns2-trace.h"
39 * set_reg_bit_32 - set bit in given 32 bits register.
50 * clear_reg_bit_32 - clear bit in given 32 bits register.
79 dma_index = readl(&pdev->adma_regs->ep_traddr) - pep->ring.dma; in cdns2_get_dma_pos()
92 if (pdev->selected_ep == ep) in cdns2_select_ep()
95 pdev->selected_ep = ep; in cdns2_select_ep()
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
11 #include <linux/dma-direction.h>
48 #define DENALI_NAND_NAME "denali-nand"
56 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
67 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
69 #define DENALI_INVALID_BANK -1
78 * Direct Addressing - the slave address forms the control information (command
84 return ioread32(denali->host + addr); in denali_direct_read()
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/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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/openbmc/qemu/hw/ssi/
H A Dxilinx_spips.c29 #include "hw/qdev-properties.h"
89 #define IXR_ALL ((1 << 13) - 1)
218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && in num_effective_busses()
219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; in num_effective_busses()
226 for (i = 0; i < s->num_cs * s->num_busses; i++) { in xilinx_spips_update_cs()
227 bool old_state = s->cs_lines_state[i]; in xilinx_spips_update_cs()
231 s->cs_lines_state[i] = new_state; in xilinx_spips_update_cs()
232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); in xilinx_spips_update_cs()
236 qemu_set_irq(s->cs_lines[i], !new_state); in xilinx_spips_update_cs()
238 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { in xilinx_spips_update_cs()
[all …]
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2016 Mentor Graphics Inc.
9 #include <linux/dma-mapping.h>
12 #include <video/imx-ipu-image-convert.h>
14 #include "ipu-prv.h"
29 * the DMA channel's parameter memory!). IDMA double-buffering is used
30 * to convert each tile back-to-back when possible (see note below
36 * +---------+-----+
37 * +-----+---+ | A | B |
39 * +-----+---+ --> +---------+-----+
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
103 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) argument
107 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) argument
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
336 /* Max number of Rx descriptors */
339 /* Max number of Tx descriptors */
342 /* Max number of allowed TCP segments for software TSO */
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
47 * for MAX faulty TPCs which reflects the cluster binning requirements
127 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
128 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
132 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
135 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
165 /* HW scrambles only bits 0-25 */
738 "AXI SPLIT SEI Status"
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/openbmc/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence USBSS DRD Driver - gadget side.
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
32 * Controller for OUT endpoints has shared on-chip buffers for all incoming
37 * Additionally the packets directed to one endpoint can block entire on-chip
59 #include <linux/dma-mapping.h>
67 #include "gadget-export.h"
68 #include "cdns3-gadget.h"
69 #include "cdns3-trace.h"
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