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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
[all …]
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM memory mapped architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
14 ARM cores may have a memory mapped architected timer, which provides up to 8
15 frames with a physical and optional virtual timer per frame.
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
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H A Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
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/openbmc/linux/arch/arm/mach-at91/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
73 bool "ARMv7 based Microchip LAN966 SoC family"
79 This enables support for ARMv7 based Microchip LAN966 SoC family.
147 bool "Periodic Interval Timer (PIT) support"
153 Timer. It has a relatively low resolution and the TC Block clocksource
157 bool "Timer Counter Blocks (TCB) support"
163 On platforms with 16-bit counters, two timer channels are combined
164 to make a single 32-bit timer.
168 bool "64-bit Periodic Interval Timer (PIT64B) support"
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/openbmc/u-boot/arch/arm/mach-highbank/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011 Calxeda, Inc.
5 * Based on arm926ejs/mx27/timer.c
10 #include <asm/arch-armv7/systimer.h>
13 #define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
18 * Start the timer
25 writel(0, &systimer_base->timer0control); in timer_init()
26 writel(SYSTIMER_RELOAD, &systimer_base->timer0load); in timer_init()
27 writel(SYSTIMER_RELOAD, &systimer_base->timer0value); in timer_init()
29 &systimer_base->timer0control); in timer_init()
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch-armv7/globaltimer.h>
20 u64 timer; in get_cpu_global_timer() local
22 u32 old = readl(&global_timer->cnt_h); in get_cpu_global_timer()
24 low = readl(&global_timer->cnt_l); in get_cpu_global_timer()
25 high = readl(&global_timer->cnt_h); in get_cpu_global_timer()
32 timer = high; in get_cpu_global_timer()
33 return (u64)((timer << 32) | low); in get_cpu_global_timer()
38 u64 timer = get_cpu_global_timer(); in get_time_us() local
40 timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); in get_time_us()
[all …]
/openbmc/u-boot/drivers/timer/
H A Dsti-timer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <timer.h>
13 #include <asm/arch-armv7/globaltimer.h>
24 struct globaltimer *global_timer = priv->global_timer; in sti_timer_get_count()
26 u64 timer; in sti_timer_get_count() local
27 u32 old = readl(&global_timer->cnt_h); in sti_timer_get_count()
30 low = readl(&global_timer->cnt_l); in sti_timer_get_count()
31 high = readl(&global_timer->cnt_h); in sti_timer_get_count()
37 timer = high; in sti_timer_get_count()
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/openbmc/qemu/docs/system/arm/
H A Dorangepi.rst1 Orange Pi PC (``orangepi-pc``)
5 based embedded computer with mainline support in both U-Boot
6 and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
15 * SMP (Quad Core Cortex-A7)
20 * Timer device (re-used from Allwinner A10)
29 * Watchdog timer
36 - Graphical output via HDMI, GPU and/or the Display Engine
37 - Audio output
38 - Hardware Watchdog
41 for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.c``
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/openbmc/u-boot/include/configs/
H A Dqemu-arm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 /* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
H A Dtegra-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2012
19 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
37 * If this varies between SoCs later, move to tegraNN-common.h
59 /*-----------------------------------------------------------------------
74 CONFIG_SYS_INIT_RAM_SIZE - \
80 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0047-corstone1000-dts-add-external-system-node.patch8 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
9 Upstream-Status: Pending [Not submitted to upstream yet]
10 ---
14 diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
16 --- a/arch/arm/dts/corstone1000.dtsi
18 @@ -122,6 +122,13 @@
19 interrupt-parent = <&gic>;
23 + compatible = "arm,corstone1000-extsys";
25 + reg-names = "reset-control", "reset-status";
26 + firmware-name = "es_flashfw.elf";
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/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-t113s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <riscv/allwinner/sunxi-d1s-t113.dtsi>
8 #include <riscv/allwinner/sunxi-d1-t113.dtsi>
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a7";
22 clock-names = "cpu";
26 compatible = "arm,cortex-a7";
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/openbmc/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
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/openbmc/u-boot/tools/patman/
H A Dtest.py1 # -*- coding: utf-8 -*-
2 # SPDX-License-Identifier: GPL-2.0+
29 Date: Thu, 28 Apr 2011 09:58:51 -0700
32 This adds functions to enable/disable clocks and reset to on-chip peripherals.
36 ‘u64 {aka long unsigned int}’ [-Wformat=]
38 BUG=chromium-os:13875
39 TEST=build U-Boot for Seaboard, boot
41 Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413
45 Signed-off-by: Simon Glass <sjg@chromium.org>
46 ---
[all …]
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dbcm2836.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
19 arm-pmu {
20 compatible = "arm,cortex-a7-pmu";
21 interrupt-parent = <&local_intc>;
26 timer {
27 compatible = "arm,armv7-timer";
[all …]
H A Dbcm2837.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
20 timer {
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
27 always-on;
31 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
10 /dts-v1/;
13 model = "XENVM-4.2";
14 compatible = "xen,xenvm-4.2", "xen,xenvm";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include "sunplus-sp7021.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt8127.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt81xx-tz-smp";
24 compatible = "arm,cortex-a7";
[all …]
/openbmc/u-boot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63148.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "brcm,brahma-b15";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6846.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
/openbmc/linux/arch/arm/mach-shmobile/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := timer.o
10 obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o
11 obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12 obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
13 obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
14 obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
15 obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
16 obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
17 obj-$(CONFIG_ARCH_R7S9210) += setup-r7s9210.o
[all …]

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