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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
14 Marvell Armada 375 Ethernet Controller (PPv2.1)
15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-slave.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
[all …]
H A Darmada-cp110-master.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 * Device Tree file for Marvell Armada CP110 Master.
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
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/openbmc/u-boot/drivers/net/
H A Dmvpp2.c2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
225 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
342 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
346 /* Per-port registers */
358 #define MVPP2_GMAC_SA_LOW_OFFS 7
374 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
[all …]