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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
14 Marvell Armada 375 Ethernet Controller (PPv2.1)
15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
21 - marvell,armada-375-pp2
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 375 family SoC
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 375 family SoC";
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/openbmc/u-boot/arch/arm/dts/
H A Darmada-375.dtsi2 * Device Tree Include file for Marvell Armada 375 family SoC
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
56 model = "Marvell Armada 375 family SoC";
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
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/openbmc/u-boot/drivers/net/
H A Dmvpp2.c2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
346 /* Per-port registers */
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
393 * relative to port->base.
491 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
493 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
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/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
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/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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