Searched +full:am65x +full:- +full:txpru0_0 +full:- +full:fw (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Suman Anna <s-anna@ti.com>13 Each Programmable Real-Time Unit and Industrial Communication Subsystem14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU17 use the Data RAMs present within the PRU-ICSS for code execution.19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy-am654-serdes.h>11 compatible = "mmio-sram";13 #address-cells = <1>;14 #size-cells = <1>;17 atf-sram@0 {21 sysfw-sram@f0000 {25 l3cache-sram@100000 {30 gic500: interrupt-controller@1800000 {[all …]