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/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun6i-a31.c222 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
237 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
250 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
252 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
262 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
[all …]
H A Dccu-sun8i-r40.c288 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
302 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
314 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
318 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
320 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
322 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
324 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
326 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
328 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
H A Dccu-sun8i-a33.c205 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
219 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
232 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
234 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
H A Dccu-sun8i-a23.c195 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
209 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
220 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
222 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
234 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
H A Dccu-sun50i-a64.c248 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
262 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
274 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
296 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
298 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
300 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
302 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
304 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
306 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
308 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
H A Dccu-sun8i-a83t.c257 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
264 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
275 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
295 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
297 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
299 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
301 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
303 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
305 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
307 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
H A Dccu-sun8i-h3.c170 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
184 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
195 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
217 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
219 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
221 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
223 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
225 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
227 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
229 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
H A Dccu-sun8i-v3s.c166 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
180 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
191 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
213 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
215 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
217 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
219 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
221 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
223 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
227 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
H A Dccu-sun50i-h6.c237 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
246 "psi-ahb1-ahb2",
281 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
294 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
304 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
326 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
336 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
346 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
349 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun50i-a100.c275 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
283 "psi-ahb1-ahb2",
320 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
334 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
344 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
355 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
365 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
368 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
371 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
374 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun50i-h616.c248 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
257 "psi-ahb1-ahb2",
292 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
303 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
312 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
326 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
337 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
347 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
350 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
353 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
[all …]
H A Dccu-sun9i-a80.c282 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
744 /* AHB1 bus gates */
745 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
747 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
749 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
751 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
753 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
755 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
757 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
924 /* AHB1 bus gates */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ahb-clk.yaml22 - allwinner,sun6i-a31-ahb1-clk
62 const: allwinner,sun6i-a31-ahb1-clk
91 ahb1@1c20054 {
93 compatible = "allwinner,sun6i-a31-ahb1-clk";
96 clock-output-names = "ahb1";
104 clocks = <&ahb1>, <&pll6d2>;
H A Dallwinner,sun4i-a10-gates-clk.yaml30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
33 - const: allwinner,sun9i-a80-ahb1-gates-clk
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml61 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
62 clock-names = "ahb1", "ahb2", "apb1", "apb2";
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dallwinner,sun6i-a31-clock-reset.yaml20 - allwinner,sun6i-a31-ahb1-reset
40 - allwinner,sun6i-a31-ahb1-reset
57 compatible = "allwinner,sun6i-a31-ahb1-reset";
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml55 lli-bus-interface-ahb1:
63 mem-bus-interface-ahb1:
114 lli-bus-interface-ahb1;
134 /* Bus interface AHB1 (AHB0) is totally tilted */
H A Dlpc1850-dmamux.txt29 lli-bus-interface-ahb1;
31 mem-bus-interface-ahb1;
/openbmc/u-boot/include/
H A Dstm32_rcc.h64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
78 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-simple-gates.c107 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
117 CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
123 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
129 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
H A Dclk-sun8i-bus-gates.c22 static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" }; in sun8i_h3_bus_gates_init()
23 enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent; in sun8i_h3_bus_gates_init() enumerator
66 clk_parent = AHB1; in sun8i_h3_bus_gates_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h35 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
158 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
159 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
160 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
272 /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
273 #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
275 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
H A Dclock_sun8i_a83t.h35 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
120 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
121 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
122 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
124 u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */
H A Dclock_sun9i.h30 u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
84 u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
91 u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Ddma.h32 #define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */

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