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/openbmc/qemu/util/
H A Dthread-context.c51 * Threads inherit the CPU affinity of the creating thread. For this in thread_context_run()
55 * Especially when QEMU is not allowed to set the affinity itself, in thread_context_run()
56 * management tools can simply set the affinity of the context thread in thread_context_run()
58 * the context inherit the CPU affinity automatically. in thread_context_run()
95 error_setg(errp, "Mixing CPU and node affinity not supported"); in thread_context_set_cpu_affinity()
118 * Note: we won't be adjusting the affinity of any thread that is still in thread_context_set_cpu_affinity()
119 * around, but only the affinity of the context thread. in thread_context_set_cpu_affinity()
123 error_setg(errp, "Setting CPU affinity failed: %s", strerror(ret)); in thread_context_set_cpu_affinity()
152 error_setg(errp, "Getting CPU affinity failed: %s", strerror(ret)); in thread_context_get_cpu_affinity()
181 error_setg(errp, "Mixing CPU and node affinity not supported"); in thread_context_set_node_affinity()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/htop/
H A Dhtop_3.3.0.bb20 affinity \
24 PACKAGECONFIG[affinity] = "--enable-affinity,--disable-affinity,,,,hwloc"
26 PACKAGECONFIG[hwloc] = "--enable-hwloc,--disable-hwloc,hwloc,,,affinity"
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h104 * choose processor with all zero affinity value as the master.
110 tst \xreg, #0xff /* Test Affinity 0 */
113 tst \xreg, #0xff /* Test Affinity 1 */
116 tst \xreg, #0xff /* Test Affinity 2 */
119 tst \xreg, #0xff /* Test Affinity 3 */
126 * choose processor with all zero affinity value as the master.
H A Dpsci.h88 /* PSCI affinity level state returned by AFFINITY_INFO */
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S96 @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
100 @ Affinity level 1 - Processors: should be in 0xf00 format.
105 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
209 @ Verify Affinity level
/openbmc/qemu/hw/intc/
H A Darm_gicv3_dist.c309 /* This GIC implementation always has affinity routing enabled, in gicd_readb()
329 /* This GIC implementation always has affinity routing enabled, in gicd_writeb()
388 * NS affinity routing is enabled, otherwise RES0 in gicd_readl()
390 * NS affinity routing is not enabled, otherwise RES0 in gicd_readl()
391 * Since for QEMU affinity routing is always enabled in gicd_readl()
407 * A3V == 1 (non-zero values of Affinity level 3 supported) in gicd_readl()
410 * LPIS == 1 (LPIs are supported if affinity routing is enabled) in gicd_readl()
509 /* RAZ/WI since affinity routing is always enabled */ in gicd_readl()
577 /* RAZ/WI since affinity routing is always enabled */ in gicd_readl()
628 * ARE is RAO/WI (affinity routin in gicd_writel()
[all...]
H A Darm_gicv3_kvm.c122 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing in kvm_gic_line_level_access()
133 /* For the KVM GICv3, affinity routing is always enabled, and the first 8
154 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 in kvm_dist_get_priority()
176 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 in kvm_dist_put_priority()
201 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 in kvm_dist_get_edge_trigger()
250 /* For the KVM GICv3, affinity routing is always enabled, and the in kvm_gic_put_line_level_bmp()
272 /* For the KVM GICv3, affinity routing is always enabled, and the in kvm_dist_getbmp()
H A Darm_gicv3_common.c449 * Top 32 bits are the affinity value of the associated CPU in arm_gicv3_common_realize()
459 cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL); in arm_gicv3_common_realize()
461 /* The CPU mp-affinity property is in MPIDR register format; squash in arm_gicv3_common_realize()
462 * the affinity bytes into 32 bits as the GICR_TYPER has them. in arm_gicv3_common_realize()
550 /* For our implementation affinity routing is always enabled */ in arm_gicv3_common_reset_hold()
/openbmc/qemu/include/hw/xen/interface/
H A Dsched.h106 * Override the current vcpu affinity by pinning it to one physical cpu or
107 * undo this override restoring the previous affinity.
111 * previous cpu affinity.
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dpsci_smp.S26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
/openbmc/qemu/include/qemu/
H A Dthread-context.h47 /* CPU affinity bitmap used for initialization. */
/openbmc/qemu/hw/ppc/
H A Dspapr_numa.c22 * Retrieves max_dist_ref_points of the current NUMA affinity.
34 * Retrieves numa_assoc_size of the current NUMA affinity.
46 * Retrieves vcpu_assoc_size of the current NUMA affinity.
58 * for the current NUMA affinity.
259 * Set NUMA machine state data based on FORM1 affinity semantics.
419 * current NUMA affinity, without the first element (size). in spapr_numa_write_assoc_lookup_arrays()
/openbmc/qemu/qapi/
H A Dqom.json901 # this SRAT Generic Port Affinity Structure. This is the same as
903 # bridge. The resulting SRAT Generic Port Affinity Structure will
1154 # @cpu-affinity: the list of host CPU numbers used as CPU affinity for
1156 # thread CPU affinity)
1158 # @node-affinity: the list of host node numbers that will be resolved
1159 # to a list of host CPU numbers used as CPU affinity. This is a
1161 # to the host nodes manually by setting @cpu-affinity.
1162 # (default: QEMU main thread affinity)
1167 'data': { '*cpu-affinity'
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/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8qxp.dtsi41 interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
H A Dfsl-imx8-ca35.dtsi56 interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
/openbmc/qemu/target/arm/tcg/
H A Dpsci.c118 /* Everything above affinity level 0 is always on. */ in arm_handle_psci_call()
164 /* Affinity levels are not supported in QEMU */ in arm_handle_psci_call()
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DMemoryRegion.v1_0_3.json185 …region content as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
232 …olatile memory as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
281 …multiple hosts as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
/openbmc/openbmc/poky/meta/recipes-core/glibc/glibc/
H A D0023-tests-Skip-2-qemu-tests-that-can-hang-in-oe-selftest.patch28 tst-sched-affinity-inheritance \
/openbmc/u-boot/include/linux/
H A Dpsci.h59 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
/openbmc/u-boot/arch/mips/include/asm/
H A Dprocessor.h80 /* Saved per-thread scheduler affinity mask */
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DMemoryRegion_v1.xml104 …multiple hosts as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
109 …olatile memory as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
114 …region content as defined in the 'Flags' field of 'Device Scoped Memory Affinity Structure' define…
/openbmc/qemu/include/hw/cxl/
H A Dcxl_cdat.h73 /* Device Scoped Memory Affinity Structure - CDAT Table 3 */
/openbmc/qemu/linux-headers/linux/
H A Dpsci.h91 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dsystem.h73 /* Read Multiprocessor Affinity Register */
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/nspr/
H A Dnspr_4.36.bb39 affinity \

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