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Searched full:zbb (Results 1 – 18 of 18) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvb.c.inc99 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
105 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
111 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
252 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
267 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
289 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
301 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
308 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
400 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
408 REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
[all …]
H A Dtrans_xthead.c.inc140 /* th.srri is an alternate encoding for rori (from Zbb) */
148 /* th.srriw is an alternate encoding for roriw (from Zbb) */
214 /* th.ff1 is an alternate encoding for clz (from Zbb) */
226 /* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */
242 /* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */
/openbmc/linux/arch/riscv/lib/
H A Dstrcmp.S42 * Variant of strcmp using the ZBB extension if available.
50 .option arch,+zbb
H A Dstrncmp.S47 * Variant of strncmp using the ZBB extension if available
53 .option arch,+zbb
H A Dstrlen.S34 * Variant of strlen using the ZBB extension if available
48 .option arch,+zbb
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml175 - const: zbb
177 The standard Zbb bit-manipulation extension for basic bit-manipulation
/openbmc/linux/Documentation/riscv/
H A Dhwprobe.rst74 * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
/openbmc/qemu/util/
H A Dcpuinfo-riscv.c112 /* Probe for Zbb: andn zero,zero,zero. */ in cpuinfo_init()
/openbmc/linux/arch/riscv/
H A DKconfig535 bool "Zbb extension support for bit manipulation instructions"
541 Adds support to dynamically detect the presence of the ZBB
544 The Zbb extension provides instructions to accelerate a number
/openbmc/linux/arch/riscv/kernel/
H A Dsys_riscv.c153 if (riscv_isa_extension_available(isainfo->isa, ZBB)) in hwprobe_isa_ext0()
H A Dcpufeature.c176 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
/openbmc/qemu/target/riscv/
H A Dinsn32.decode766 # *** RV32 Zbb/Zbkb Standard Extension ***
781 # *** RV32 extra Zbb Standard Extension ***
799 # *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
814 # *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
H A Dcpu.c142 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
1520 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_onereg.c43 KVM_ISA_EXT_ARR(ZBB),
/openbmc/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c723 {"zbb", .feature = KVM_RISCV_ISA_EXT_ZBB, .regs = zbb_regs, .regs_n = ARRAY_SIZE(zbb_regs),}
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c397 warn_report(warn_msg, "zbb"); in riscv_cpu_validate_b()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c292 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc224 /* Zbb: Bit manipulation extension, basic bit manipulation */