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/openbmc/linux/Documentation/devicetree/bindings/mips/
H A Dcpus.yaml26 - ingenic,xburst-mxu1.0
27 - ingenic,xburst-fpu1.0-mxu1.1
28 - ingenic,xburst-fpu2.0-mxu2.0
57 - ingenic,xburst-mxu1.0
58 - ingenic,xburst-fpu1.0-mxu1.1
59 - ingenic,xburst-fpu2.0-mxu2.0
100 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
108 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
/openbmc/linux/Documentation/devicetree/bindings/mips/ingenic/
H A Ddevices.yaml7 title: Ingenic XBurst based Platforms
13 Devices with a Ingenic XBurst CPU shall have the following properties.
/openbmc/linux/arch/mips/kernel/
H A Dcpu-probe.c1753 * XBurst misses a config2 register, so config3 decode was skipped in in cpu_probe_ingenic()
1758 /* XBurst does not implement the CP0 counter. */ in cpu_probe_ingenic()
1762 /* XBurst has virtually tagged icache */ in cpu_probe_ingenic()
1767 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ in cpu_probe_ingenic()
1771 * The XBurst core by default attempts to avoid branch target in cpu_probe_ingenic()
1781 * The config0 register in the XBurst CPUs with a processor ID of in cpu_probe_ingenic()
1795 * The config0 register in the XBurst CPUs with a processor ID of in cpu_probe_ingenic()
1813 /* XBurst®1 with MXU2.0 SIMD ISA */ in cpu_probe_ingenic()
1818 __cpu_name[cpu] = "Ingenic XBurst"; in cpu_probe_ingenic()
1821 /* XBurst®2 with MXU2.1 SIMD ISA */ in cpu_probe_ingenic()
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dingenic,sysost.yaml7 title: SYSOST in Ingenic XBurst family SoCs
/openbmc/u-boot/doc/
H A DREADME.mips52 * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dingenic,vpu.yaml11 Ingenic is a second Xburst MIPS CPU very similar to the main core.
/openbmc/u-boot/arch/mips/mach-jz47xx/
H A Dstart.S3 * Startup Code for MIPS32 XBURST CPU-core
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
191 #define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
/openbmc/linux/drivers/irqchip/
H A Dirq-ingenic.c4 * Ingenic XBurst platform IRQ support
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
H A Djz4740.dtsi16 compatible = "ingenic,xburst-mxu1.0";
H A Djz4725b.dtsi16 compatible = "ingenic,xburst-mxu1.0";
H A Dx1000.dtsi17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
H A Djz4770.dtsi16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
H A Dx1830.dtsi17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
/openbmc/linux/drivers/clocksource/
H A Dingenic-timer.c337 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online", in ingenic_tcu_init()
H A Dingenic-sysost.c3 * Ingenic XBurst SoCs SYSOST clocks driver
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dinst.h276 * func field for special2 MXU opcodes (Ingenic XBurst MXU).
284 * op field for special2 MXU LX opcodes (Ingenic XBurst MXU).
/openbmc/qemu/target/mips/tcg/
H A Dmxu_translate.c2 * Ingenic XBurst Media eXtension Unit (MXU) translation routines.
14 * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
29 * video processing applications. MXU instruction set is used in Xburst family
351 * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit