| /openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
| H A D | regs-pinctrl.h | 158 #define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14)
160 #define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12)
162 #define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10)
164 #define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8)
166 #define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6)
168 #define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4)
170 #define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2)
172 #define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0)
175 #define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24)
177 #define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22)
[all …]
|
| /openbmc/linux/arch/x86/crypto/ |
| H A D | serpent-avx2-asm_64.S | 51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
72 vpxor x3, x0, x0; \
[all …]
|
| H A D | serpent-avx-x86_64-asm_64.S | 51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
72 vpxor x3, x0, x0; \
[all …]
|
| H A D | serpent-sse2-i586-asm_32.S | 42 #define K(x0, x1, x2, x3, x4, i) \ argument
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
72 pslld $7, x3; \
74 por x4, x3; \
78 pxor x3, x0; \
79 pxor x3, x2; \
[all …]
|
| H A D | serpent-sse2-x86_64-asm_64.S | 41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-mx5/ |
| H A D | crm_regs.h | 91 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
93 #define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
95 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
97 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
99 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
101 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
141 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-mx35/ |
| H A D | crm_regs.h | 17 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
19 #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
21 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
28 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
116 #define MXC_CCM_CGR_CG_MASK 0x3
120 #define MXC_CCM_CGR_CG_ON 0x3
123 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
125 #define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
127 #define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
129 #define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
[all …]
|
| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-serdes.h | 16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
26 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
31 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
36 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
41 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
46 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
51 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
56 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
61 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
|
| /openbmc/linux/include/dt-bindings/mux/ |
| H A D | ti-serdes.h | 22 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
27 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
32 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
37 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
42 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
47 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
52 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
57 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
62 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
67 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
|
| /openbmc/linux/drivers/pinctrl/berlin/ |
| H A D | berlin-bg4ct.c | 19 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
22 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
26 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
27 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
31 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */
32 BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09,
36 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */
37 BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c,
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */
42 BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f,
[all …]
|
| H A D | pinctrl-as370.c | 19 BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
23 BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
27 BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
30 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO2 */
32 BERLIN_PINCTRL_GROUP("I2S1_DO1", 0x0, 0x3, 0x09,
35 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO3 */
37 BERLIN_PINCTRL_GROUP("I2S1_DO2", 0x0, 0x3, 0x0c,
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO4 */
43 BERLIN_PINCTRL_GROUP("I2S1_DO3", 0x0, 0x3, 0x0f,
47 BERLIN_PINCTRL_FUNCTION(0x3, "spdifib"), /* SPDIFIB */
[all …]
|
| H A D | berlin-bg2q.c | 20 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
24 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
27 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
30 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
31 BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09,
34 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
35 BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c,
39 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"),
43 BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f,
50 BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12,
[all …]
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | imx7ulp-pinfunc.h | 29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
36 #define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1
43 #define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1
57 #define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1
64 #define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1
71 #define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1
78 #define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1
84 #define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1
92 #define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1
98 #define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1
[all …]
|
| H A D | imx7d-pinfunc.h | 21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
31 #define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
32 #define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
35 #define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
38 #define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
39 #define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
42 #define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
46 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
47 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
[all …]
|
| /openbmc/linux/crypto/ |
| H A D | serpent_generic.c | 27 #define loadkeys(x0, x1, x2, x3, i) \ argument
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
30 #define storekeys(x0, x1, x2, x3, i) \ argument
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
33 #define store_and_load_keys(x0, x1, x2, x3, s, l) \ argument
34 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
36 #define K(x0, x1, x2, x3, i) ({ \ argument
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
41 #define LK(x0, x1, x2, x3, x4, i) ({ \ argument
44 x3 ^= x2; x1 ^= x2; \
[all …]
|
| /openbmc/linux/arch/arm64/lib/ |
| H A D | tishift.S | 12 mov x3, #64
13 sub x3, x3, x2
14 cmp x3, #0
17 lsr x3, x0, x3
19 orr x1, x1, x3
34 mov x3, #64
35 sub x3, x3, x2
36 cmp x3, #0
39 lsl x3, x1, x3
41 orr x0, x0, x3
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | crm_regs.h | 145 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
146 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
158 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
159 #define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
161 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
162 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
164 #define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
165 #define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
194 #define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
197 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
[all …]
|
| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx7ulp-pinfunc.h | 41 #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
49 #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
57 #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
71 #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
79 #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
87 #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
95 #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
102 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
110 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
119 #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
[all …]
|
| H A D | imx7d-pinfunc.h | 17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
28 #define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
31 #define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
34 #define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
35 #define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
38 #define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
42 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
43 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
[all …]
|
| /openbmc/bmcweb/include/ |
| H A D | http_utility.hpp | 5 #include <boost/spirit/home/x3/char/char.hpp>
6 #include <boost/spirit/home/x3/char/char_class.hpp>
7 #include <boost/spirit/home/x3/core/parse.hpp>
8 #include <boost/spirit/home/x3/directive/no_case.hpp>
9 #include <boost/spirit/home/x3/directive/omit.hpp>
10 #include <boost/spirit/home/x3/numeric/uint.hpp>
11 #include <boost/spirit/home/x3/operator/alternative.hpp>
12 #include <boost/spirit/home/x3/operator/kleene.hpp>
13 #include <boost/spirit/home/x3/operator/optional.hpp>
14 #include <boost/spirit/home/x3/operator/plus.hpp>
[all …]
|
| /openbmc/qemu/tests/tcg/i386/ |
| H A D | test-i386-fpatan.c | 11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
22 { -0.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
23 { -0.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
44 …{ 0x5.51ee0c58f7fbf45p-4L, -0x3.a11abadbd605d354p-4L, -0x9.942ec5a1e6d706ap-4L, -0x9.942ec5a1e6d70…
52 …{ -0x2.c18975d92e49e91p+72L, 0xa.d41581f0036d233p-4L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d…
[all …]
|
| H A D | test-i386-fyl2xp1.c | 34 …{ 0x3.311f29ec8b38ef74p-4L, -0x3.9865a5505c3ae018p+8924L, -0xf.188d6a2bba06e17p+8920L, -0xf.188d6a…
39 …{ -0x4.64109ab4700cf108p-4L, 0x6.b8d96cb8e5f2d648p+6524L, -0x3.1c6e7c0e4e7a72cp+6524L, -0x3.1c6e7c…
40 …{ 0x3.e104f8db9c02bf08p-4L, -0x9.7b905723db3fe54p+10116L, -0x2.f83eb6c0529e814p+10116L, -0x2.f83eb…
41 …{ -0x3.906c6b45a9367874p-4L, -0x3.b4f349ff071caa64p-1868L, 0x1.5901debf0c548972p-1868L, 0x1.5901de…
43 …{ -0x1.422d05691d16c3c2p-4L, -0x3.b7afc1088aafbb28p+8056L, 0x7.07a7a145b32d0108p+8052L, 0x7.07a7a1…
44 …{ 0x3.005497260bfe3efcp-4L, 0x2.70b5fc4ea650b9d4p+13164L, 0x9.af1b9b78be96p+13160L, 0x9.af1b9b78be…
45 …{ -0x3.06e1d8ce558315f4p-4L, 0xd.35a31147278a276p+13452L, -0x3.ff1a81342b225bf4p+13452L, -0x3.ff1a…
49 …{ -0x3.f7c63bee23b61aep-4L, -0x1.a4746c335dbffc62p+13532L, 0xa.ce1e8b95a3cf783p+13528L, 0xa.ce1e8b…
51 …{ -0x4.0c0f16fccf171958p-4L, -0x3.809f02e6f0a4a7ccp-632L, 0x1.793819991e50c69p-632L, 0x1.793819991…
55 …{ -0x2.975eb02ec54042c4p-4L, -0xe.5f17872c08b122dp+7300L, 0x3.a9ce29cce0f873bp+7300L, 0x3.a9ce29cc…
[all …]
|
| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-pinfunc.h | 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
[all …]
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| /openbmc/linux/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sun4i-a10.c | 25 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
34 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
43 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
52 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
61 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
69 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
77 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
85 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
93 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
101 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
[all …]
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| /openbmc/linux/include/linux/mfd/syscon/ |
| H A D | imx6q-iomuxc-gpr.h | 26 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
30 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
31 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
35 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
39 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
[all …]
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