| /openbmc/linux/drivers/staging/greybus/ |
| H A D | audio_apbridgea.h | 13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | rt5682.txt | 50 - #clock-cells : Should be set to '<1>', wclk and bclk sources provided.
89 clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
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| H A D | ti,tlv320adc3xxx.yaml | 56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
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| H A D | dialog,da7219.yaml | 60 Name given for DAI WCLK and BCLK outputs.
212 clock-output-names = "da7219-dai-wclk", "da7219-dai-bclk";
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| H A D | realtek,rt5682s.yaml | 140 clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
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| /openbmc/linux/sound/soc/amd/ |
| H A D | acp-da7219-max98357a.c | 76 da7219_dai_wclk = devm_clk_get(component->dev, "da7219-dai-wclk"); in cz_da7219_init()
112 * Set wclk to 48000 because the rate constraint of this driver is in da7219_clk_enable()
158 rt5682_dai_wclk = devm_clk_get(component->dev, "rt5682-dai-wclk"); in cz_rt5682_init()
197 * Set wclk to 48000 because the rate constraint of this driver is in rt5682_clk_enable()
204 dev_err(rtd->dev, "Error setting wclk rate: %d\n", ret); in rt5682_clk_enable()
214 dev_err(rtd->dev, "can't enable wclk %d\n", ret); in rt5682_clk_enable()
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| H A D | acp3x-rt5682-max9836.c | 97 rt5682_dai_wclk = clk_get(component->dev, "rt5682-dai-wclk"); in acp3x_5682_init()
136 dev_err(rtd->dev, "can't enable wclk %d\n", ret); in rt5682_clk_enable()
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | samsung,exynos4210-csis.yaml | 92 samsung,csis-wclk:
167 samsung,csis-wclk;
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | da7219.c | 1429 struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX]; in da7219_set_dai_tdm_slot() local
1476 sr = clk_get_rate(wclk); in da7219_set_dai_tdm_slot()
1489 "Failed to set TDM BCLKs per WCLK %d: %d\n", in da7219_set_dai_tdm_slot()
1565 struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX]; in da7219_hw_params() local
1600 if (da7219->master && wclk) { in da7219_hw_params()
1601 ret = clk_set_rate(wclk, sr); in da7219_hw_params()
1604 "Failed to set WCLK SR %lu: %d\n", sr, ret); in da7219_hw_params()
1655 "Failed to set BCLKs per WCLK %d: %d\n", in da7219_hw_params()
1779 pdata->dai_clk_names[DA7219_DAI_WCLK_IDX] = "da7219-dai-wclk"; in da7219_fw_to_pdata()
2086 * derived from multiple parent WCLK rates (BCLK rates are set as a in da7219_bclk_round_rate()
[all …]
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| H A D | rt5682.c | 2664 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_recalc_rate()
2687 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_round_rate()
2717 * Whether the wclk's parent clk (mclk) exists or not, please ensure in rt5682_wclk_set_rate()
2718 * it is fixed or set to 48MHz before setting wclk rate. It's a in rt5682_wclk_set_rate()
2726 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", in rt5682_wclk_set_rate()
2808 * BCLK rates are set as a multiplier of WCLK in HW. in rt5682_bclk_round_rate()
2809 * We don't allow changing the parent WCLK. We just do in rt5682_bclk_round_rate()
2810 * some rounding down based on the parent WCLK rate in rt5682_bclk_round_rate()
2875 /* Make MCLK the parent of WCLK */ in rt5682_register_dai_clks()
2883 /* Make WCLK the parent of BCLK */ in rt5682_register_dai_clks()
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| H A D | rt5682s.c | 38 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
2601 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682s_wclk_recalc_rate()
2624 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682s_wclk_round_rate()
2650 * Whether the wclk's parent clk (mclk) exists or not, please ensure in rt5682s_wclk_set_rate()
2651 * it is fixed or set to 48MHz before setting wclk rate. It's a in rt5682s_wclk_set_rate()
2659 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", in rt5682s_wclk_set_rate()
2733 * BCLK rates are set as a multiplier of WCLK in HW. in rt5682s_bclk_round_rate()
2734 * We don't allow changing the parent WCLK. We just do in rt5682s_bclk_round_rate()
2735 * some rounding down based on the parent WCLK rate in rt5682s_bclk_round_rate()
2799 /* Make MCLK the parent of WCLK */ in rt5682s_register_dai_clks()
[all …]
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| H A D | rt5682-i2c.c | 38 .dai_clk_names[RT5682_DAI_WCLK_IDX] = "rt5682-dai-wclk",
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| H A D | tlv320aic31xx.c | 570 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
754 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
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| H A D | da9055.c | 1203 /* By default only 32 BCLK per WCLK is supported */ in da9055_set_dai_fmt()
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| /openbmc/linux/include/dt-bindings/sound/ |
| H A D | tlv320adc3xxx.h | 19 #define ADC3XXX_GPIO_SECONDARY_WCLK 9 /* Codec interface secondary WCLK */
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| /openbmc/linux/sound/soc/amd/acp/ |
| H A D | acp-mach.h | 62 struct clk *wclk; member
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| H A D | acp-mach-common.c | 77 clk_set_rate(drvdata->wclk, srate); in acp_clk_enable()
80 return clk_prepare_enable(drvdata->wclk); in acp_clk_enable()
129 drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk"); in acp_card_rt5682_init()
214 clk_disable_unprepare(drvdata->wclk); in acp_card_shutdown()
355 drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk"); in acp_card_rt5682s_init()
474 clk_set_rate(drvdata->wclk, srate); in acp_card_rt5682s_hw_params()
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | mrc_util.h | 70 WCLK, enumerator
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| H A D | mrc_util.c | 695 * This function will program the WCLK delays based on an absolute
771 * This function will return the amout of WCLK delay on the given
1404 case WCLK: in print_timings_internal()
1434 case WCLK: in print_timings_internal()
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| H A D | smc.c | 1545 * (align WCLK and WDQS).
1646 /* Initialize the starting delay to WCLK */ in wr_level()
2078 * patterns pass. This is because WDQS will be aligned to WCLK by the
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| /openbmc/linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-dc.c | 55 #define WCLK 0xc9 macro
125 if (opcode == WCLK) { in dc_write_tmpl()
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| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779g0-white-hawk-ard-audio-da7212.dtso | 23 * | SSI_WS_V pin13 |<----->| pin3 WCLK |
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| /openbmc/linux/drivers/media/platform/samsung/exynos4-is/ |
| H A D | mipi-csis.c | 752 "samsung,csis-wclk"); in s5pcsis_parse_dt()
874 dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n", in s5pcsis_probe()
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| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | cx23885-cards.c | 1590 /* GPIO-22 IIS WCLK */ in cx23885_gpio_setup()
1744 /* GPIO-22 I2S WCLK */ in cx23885_gpio_setup()
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| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos4412-midas.dtsi | 489 samsung,csis-wclk;
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