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Searched full:vdw (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/freescale/common/
H A Dics307_clk.c46 * the result will be retuned with component RDW, VDW, OD, TTL,
52 unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; in ics307_sysclk_calculator() local
61 /* Calculate the VDW */ in ics307_sysclk_calculator()
62 vdw = out_freq * 1000 * od * rdw / (input_freq * 2); in ics307_sysclk_calculator()
63 if (vdw > MAX_VDW) in ics307_sysclk_calculator()
64 vdw = MAX_VDW; in ics307_sysclk_calculator()
65 if (vdw < MIN_VDW) in ics307_sysclk_calculator()
68 tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); in ics307_sysclk_calculator()
78 s_vdw = vdw; in ics307_sysclk_calculator()
91 debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, in ics307_sysclk_calculator()
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/openbmc/linux/drivers/clk/versatile/
H A Dclk-icst.h9 ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */
10 ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */
12 ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */
13 ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */
H A Dclk-icst.c164 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
174 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
184 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
192 pr_err("ICST error: tried to set bit 8 of VDW\n"); in vco_set()
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
459 /* Maximum 50 MHz, VDW = 192 */
/openbmc/u-boot/cmd/
H A Duniverse.c119 …e_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int size, int vam, int pms, int vdw) in universe_pci_slave_window() argument
172 switch (vdw & VME_FLAG_Dxx) { in universe_pci_slave_window()
303 ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, pms = 0, vdw = 0; in do_universe() local
320 vdw = simple_strtoul(argv[7], NULL, 16); in do_universe()
334 printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx pms=%02lx vdw=%02lx\n", in do_universe()
335 addr1, addr2, size, vam, pms, vdw); in do_universe()
336 universe_pci_slave_window(addr1, addr2, size, vam, pms, vdw); in do_universe()
353 "universe pci [pci_addr] [vme_addr] [size] [vam] [pms] [vdw]\n"
364 " [vdw] = VMEbus Maximum Datawidth: 01 -> D8 Data Width\n"
H A Dtsi148.c132 int size, int vam, int vdw) in tsi148_pci_slave_window() argument
188 switch (vdw & VME_FLAG_Dxx) { in tsi148_pci_slave_window()
387 ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0; in do_tsi148() local
402 vdw = simple_strtoul(argv[6], NULL, 16); in do_tsi148()
436 printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n", in do_tsi148()
437 addr1, addr2, size, vam, vdw); in do_tsi148()
438 tsi148_pci_slave_window(addr1, addr2, size, vam, vdw); in do_tsi148()
454 "tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
469 " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Darm,syscon-icst.yaml25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
35 Hardware variant RDW OD VDW