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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_easrc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma/imx-dma.h>
88 #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
89 #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
91 #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
92 #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
94 #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
95 #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
98 #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
100 #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \ argument
[all …]
/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
[all …]
H A Dhantro_g1_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
[all …]
H A Drockchip_vpu2_hw_h264_dec.c1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
[all …]
H A Dhantro_g1_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24)
17 #define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18)
18 #define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
19 #define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16)
20 #define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15)
21 #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
22 #define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13)
23 #define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12)
24 #define G1_REG_INTERRUPT_DEC_IRQ BIT(8)
[all …]
/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
19 * bit 15:0 sequence number
21 u32 stride; /* bit 31:16 write stride
22 * bit 15:0 read stride
29 /* mSGDMA descriptor control field bit definitions
32 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
33 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
34 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
[all …]
H A Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
55 /* MAC Command_Config Register Bit Definitions
57 #define MAC_CMDCFG_TX_ENA BIT(0)
58 #define MAC_CMDCFG_RX_ENA BIT(1)
59 #define MAC_CMDCFG_XON_GEN BIT(2)
60 #define MAC_CMDCFG_ETH_SPEED BIT(3)
61 #define MAC_CMDCFG_PROMIS_EN BIT(4)
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dstm32-dfsdm.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
15 * STM32 DFSDM - global register map
18 * ----------------------------------------------------------
20 * ----------------------------------------------------------
22 * ----------------------------------------------------------
24 * ----------------------------------------------------------
26 * ----------------------------------------------------------
28 * ----------------------------------------------------------
30 * ----------------------------------------------------------
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
17 #define SUN6I_CSI_EN_VER_EN BIT(30)
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
19 #define SUN6I_CSI_EN_SRAM_PWDN BIT(8)
20 #define SUN6I_CSI_EN_PTN_START BIT(4)
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
22 #define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)
23 #define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)
[all …]
/openbmc/linux/lib/
H A Datomic64_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun8i-di/
H A Dsun8i-di.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-mem2mem.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/videobuf2-dma-contig.h>
18 #define DEINTERLACE_NAME "sun8i-di"
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
25 #define DEINTERLACE_FRM_CTRL_WB_EN BIT(2)
26 #define DEINTERLACE_FRM_CTRL_OUT_CTRL BIT(11)
[all …]
/openbmc/linux/sound/soc/sunxi/
H A Dsun4i-spdif.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */ argument
32 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
33 #define SUN4I_SPDIF_CTL_GEN BIT(1)
34 #define SUN4I_SPDIF_CTL_RESET BIT(0)
37 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
38 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
39 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
40 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4) argument
46 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
[all …]
/openbmc/linux/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2017-2018, Arm Ltd.
15 #define ARM_SPE_NEED_MORE_BYTES -1
16 #define ARM_SPE_BAD_PACKET -2
72 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0)) argument
73 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48) argument
75 #define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63) argument
76 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61) argument
77 #define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62) argument
78 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56) argument
[all …]
/openbmc/linux/drivers/power/supply/
H A Dbq24190_charger.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/extcon-provider.h>
24 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
26 #define BQ24190_REG_ISC_VINDPM_MASK (BIT(6) | BIT(5) | BIT(4) | \
27 BIT(3))
29 #define BQ24190_REG_ISC_IINLIM_MASK (BIT(2) | BIT(1) | BIT(0))
32 #define BQ24190_REG_POC 0x01 /* Power-On Configuration */
33 #define BQ24190_REG_POC_RESET_MASK BIT(7)
35 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
37 #define BQ24190_REG_POC_CHG_CONFIG_MASK (BIT(5) | BIT(4))
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
28 #define PPI_STARTPPI 0x0104 /* START control bit */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
45 #define VP_CTRL_MSF BIT(0) /* Magic square in RGB666 */
46 #define VP_CTRL_VTGEN BIT(4) /* Use chip clock for timing */
47 #define VP_CTRL_EVTMODE BIT(5) /* Event mode */
48 #define VP_CTRL_RGB888 BIT(8) /* RGB888 mode */
49 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ argument
50 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
61 /* struct sunxi_priv_data - hold all sunxi private data
69 * @mux_handle: Internal pointer used by mdio-mux lib
147 * co-packaged AC200 chip instead.
181 #define EMAC_DUPLEX_FULL BIT(0)
182 #define EMAC_LOOPBACK BIT(1)
[all …]
/openbmc/linux/fs/xfs/libxfs/
H A Dxfs_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * XFS bit manipulation routines.
14 * masks with n high/low bits set, 64-bit values
18 return (uint64_t)-1 << (64 - (n)); in xfs_mask64hi()
22 return ((uint32_t)1 << (n)) - 1; in xfs_mask32lo()
26 return ((uint64_t)1 << (n)) - 1; in xfs_mask64lo()
29 /* Get high bit set out of 32-bit argument, -1 if none set */
30 static inline int xfs_highbit32(uint32_t v) in xfs_highbit32() argument
32 return fls(v) - 1; in xfs_highbit32()
35 /* Get high bit set out of 64-bit argument, -1 if none set */
[all …]
/openbmc/u-boot/drivers/mtd/
H A Drenesas_rpc_hf.c1 // SPDX-License-Identifier: GPL-2.0
23 #define RPC_CMNCR_MD BIT(31)
43 #define RPC_DRCR_SSLN BIT(24)
44 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) argument
45 #define RPC_DRCR_RCF BIT(9)
46 #define RPC_DRCR_RBE BIT(8)
47 #define RPC_DRCR_SSLE BIT(0)
54 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) argument
55 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) argument
69 #define RPC_DRENR_DME BIT(15)
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
31 /* GEMAC Bit definitions */
32 #define EMAC_IEVENT_HBERR BIT(31)
33 #define EMAC_IEVENT_BABR BIT(30)
34 #define EMAC_IEVENT_BABT BIT(29)
35 #define EMAC_IEVENT_GRA BIT(28)
36 #define EMAC_IEVENT_TXF BIT(27)
37 #define EMAC_IEVENT_TXB BIT(26)
38 #define EMAC_IEVENT_RXF BIT(25)
[all …]
/openbmc/u-boot/drivers/spi/
H A Drenesas_rpc_spi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <dt-structs.h>
20 #define RPC_CMNCR_MD BIT(31)
21 #define RPC_CMNCR_SFDE BIT(24)
33 #define RPC_CMNCR_CPHAT BIT(6)
34 #define RPC_CMNCR_CPHAR BIT(5)
35 #define RPC_CMNCR_SSLP BIT(4)
36 #define RPC_CMNCR_CPOL BIT(3)
45 #define RPC_DRCR_SSLN BIT(24)
46 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) argument
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov5648.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/v4l2-fwnode.h>
19 #include <media/v4l2-image-sizes.h>
20 #include <media/v4l2-mediabus.h>
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
34 #define OV5648_SW_RESET_RESET BIT(0)
52 #define OV5648_PAD_PK_PD_DATO_EN BIT(7)
55 #define OV5648_PAD_PK_FREX_N BIT(1)
[all …]

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