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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 TCON TOP
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 TCON TOPs main purpose is to configure whole display pipeline. It
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/clock/sun8i-tcon-top.h>
28 int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon) in sun8i_tcon_top_set_hdmi_src() argument
34 if (!sun8i_tcon_top_node_is_tcon_top(dev->of_node)) { in sun8i_tcon_top_set_hdmi_src()
35 dev_err(dev, "Device is not TCON TOP!\n"); in sun8i_tcon_top_set_hdmi_src()
36 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
39 if (tcon < 2 || tcon > 3) { in sun8i_tcon_top_set_hdmi_src()
40 dev_err(dev, "TCON index must be 2 or 3!\n"); in sun8i_tcon_top_set_hdmi_src()
41 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
44 spin_lock_irqsave(&tcon_top->reg_lock, flags); in sun8i_tcon_top_set_hdmi_src()
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/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h6 * SPDX-License-Identifier: GPL-2.0+
203 u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
204 u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
206 u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
207 u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
209 u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
281 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
292 #define MBUS_CLK_M(m) (((m)-1) << 0)
302 #define DRAM_CLK_M(m) (((m)-1) << 0)
305 #define CCM_MMC_CTRL_M(x) ((x) - 1)
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
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/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/clock/sun8i-tcon-top.h>
49 #include <dt-bindings/reset/sun8i-r40-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/thermal/thermal.h>
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/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-r40.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-r40.h"
37 .hw.init = CLK_HW_INIT("pll-cpu",
49 * With sigma-delta modulation for fractional-N on the audio PLL,
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
88 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
120 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
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H A Dccu-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
75 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
107 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
129 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
147 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
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H A Dccu-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
146 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
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/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c22 #include "qemu/error-report.h"
27 #include "hw/qdev-core.h"
29 #include "hw/char/serial-mm.h"
31 #include "hw/usb/hcd-ehci.h"
34 #include "hw/arm/allwinner-r40.h"
35 #include "hw/misc/allwinner-r40-dramc.h"
36 #include "target/arm/cpu-qom.h"
87 { "d-engine", 0x01000000, 4 * MiB },
88 { "d-inter", 0x01400000, 128 * KiB },
96 { "usb0-otg", 0x01c13000, 4 * KiB },
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