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/openbmc/linux/arch/arm64/
H A DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
9 This enables support for the Actions Semiconductor S900 SoC family.
12 bool "Allwinner sunxi 64-bit SoC Family"
27 Soc family.
30 bool "Apple Silicon SoC family"
33 This enables support for Apple's in-house ARM SoC family, starting
37 bool "Broadcom SoC Support"
52 This enables support for the Broadcom BCM2837 and BCM2711 SoC.
56 bool "Broadcom iProc SoC Family"
64 bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
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/openbmc/qemu/hw/arm/
H A Dxlnx-zcu102.c20 #include "hw/arm/xlnx-zynqmp.h"
23 #include "qemu/error-report.h"
33 XlnxZynqMPState soc; member
43 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
49 XlnxZCU102 *s = ZCU102_MACHINE(obj); in OBJECT_DECLARE_SIMPLE_TYPE() local
51 return s->secure; in OBJECT_DECLARE_SIMPLE_TYPE()
56 XlnxZCU102 *s = ZCU102_MACHINE(obj); in zcu102_set_secure() local
58 s->secure = value; in zcu102_set_secure()
63 XlnxZCU102 *s = ZCU102_MACHINE(obj); in zcu102_get_virt() local
65 return s->virt; in zcu102_get_virt()
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H A Dfby35.c5 * file in the top-level directory.
12 #include "sysemu/block-backend.h"
14 #include "hw/qdev-clock.h"
71 static void fby35_bmc_init(Fby35State *s) in fby35_bmc_init() argument
73 AspeedSoCState *soc; in fby35_bmc_init() local
75 object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); in fby35_bmc_init()
76 soc = ASPEED_SOC(&s->bmc); in fby35_bmc_init()
78 memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory", in fby35_bmc_init()
80 memory_region_init_ram(&s->bmc_dram, OBJECT(&s->bmc), "bmc-dram", in fby35_bmc_init()
83 object_property_set_int(OBJECT(&s->bmc), "ram-size", FBY35_BMC_RAM_SIZE, in fby35_bmc_init()
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H A Dkzm.c5 * Written by Hans at OK-Labs
12 * KZM-ARM11-01 evaluation board, with a Freescale
13 * i.MX31 SoC
18 #include "hw/arm/fsl-imx31.h"
21 #include "qemu/error-report.h"
22 #include "exec/address-spaces.h"
25 #include "hw/char/serial-mm.h"
31 * 0x00000000-0x7fffffff See i.MX31 SOC for support
32 * 0x80000000-0x8fffffff RAM EMULATED
33 * 0x90000000-0x9fffffff RAM EMULATED
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H A Dexynos4_boards.c2 * Samsung exynos4 SoC based boards emulation
27 #include "qemu/error-report.h"
31 #include "exec/address-spaces.h"
34 #include "hw/qdev-properties.h"
37 #include "target/arm/cpu-qom.h"
48 Exynos4210State soc; member
77 SysBusDevice *s; in lan9215_init() local
83 s = SYS_BUS_DEVICE(dev); in lan9215_init()
84 sysbus_realize_and_unref(s, &error_fatal); in lan9215_init()
85 sysbus_mmio_map(s, 0, base); in lan9215_init()
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H A Draspi.c12 * See the COPYING file in the top-level directory.
24 #include "qemu/error-report.h"
30 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
44 BCM283XState soc; member
49 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
141 info->smp_loader_start, smpboot, fixupcontext); in write_smpboot()
148 * The mechanism for doing the spin-table is also entirely different. in write_smpboot64()
149 * We must have four 64-bit fields at absolute addresses in write_smpboot64()
175 arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, in write_smpboot64()
189 cpu_set_pc(cs, info->smp_loader_start); in reset_secondary()
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H A Db-l475e-iot01a.c2 * B-L475E-IOT01A Discovery Kit machine
3 * (B-L475E-IOT01A IoT Node)
5 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
6 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * See the COPYING file in the top-level directory.
21 * Discovery kit for IoT node, multi-channel communication with STM32L4.
22 * https://www.st.com/en/evaluation-tools/b-l475e-iot01a.html#documentation
28 #include "hw/qdev-properties.h"
29 #include "qemu/error-report.h"
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-devices-soc5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
30 this will contain the JEDEC JEP106 manufacturer’s identification
34 This manufacturer’s identification code is defined by one
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/openbmc/linux/drivers/pcmcia/
H A Dsa1111_generic.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <asm/mach-types.h>
70 struct sa1111_pcmcia_socket *s = to_skt(skt); in sa1111_pcmcia_socket_state() local
71 u32 status = readl_relaxed(s->dev->mapbase + PCSR); in sa1111_pcmcia_socket_state()
73 switch (skt->nr) { in sa1111_pcmcia_socket_state()
75 state->detect = status & PCSR_S0_DETECT ? 0 : 1; in sa1111_pcmcia_socket_state()
76 state->ready = status & PCSR_S0_READY ? 1 : 0; in sa1111_pcmcia_socket_state()
77 state->bvd1 = status & PCSR_S0_BVD1 ? 1 : 0; in sa1111_pcmcia_socket_state()
78 state->bvd2 = status & PCSR_S0_BVD2 ? 1 : 0; in sa1111_pcmcia_socket_state()
79 state->wrprot = status & PCSR_S0_WP ? 1 : 0; in sa1111_pcmcia_socket_state()
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dqts-filter.sh8 sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
13 # $1: SoC type
19 soc="$1"
26 /* SPDX-License-Identifier: BSD-3-Clause */
38 ${in_bsp_dir}/generated/iocsr_config_${soc}.h |
39 grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
43 # Retrieve the scan chain config and zap the ad-hoc length encoding
45 ${in_bsp_dir}/generated/iocsr_config_${soc}.c |
46 sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
57 # $1: SoC type
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/openbmc/qemu/hw/riscv/
H A Dspike.c2 * QEMU RISC-V Spike Board
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This provides a RISC-V Board with the following devices:
26 #include "qemu/error-report.h"
51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, in create_fdt() argument
59 MachineState *ms = MACHINE(s); in create_fdt()
68 fdt = ms->fdt = create_device_tree(&fdt_size); in create_fdt()
74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); in create_fdt()
75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); in create_fdt()
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H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
95 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, in create_fdt() argument
98 MachineState *ms = MACHINE(s); in create_fdt()
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
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H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
45 #include "hw/platform-bus.h"
54 #include "hw/pci-host/gpex.h"
56 #include "hw/acpi/aml-build.h"
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/openbmc/qemu/tests/qtest/
H A Daspeed_gpio-test.c29 #include "libqtest-single.h"
38 QTestState *s = (QTestState *)data; in test_set_colocated_pins() local
41 * gpioV4-7 occupy bits within a single 32-bit value, so we want to make in test_set_colocated_pins()
44 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); in test_set_colocated_pins()
45 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); in test_set_colocated_pins()
46 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); in test_set_colocated_pins()
47 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); in test_set_colocated_pins()
48 g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); in test_set_colocated_pins()
49 g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); in test_set_colocated_pins()
50 g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); in test_set_colocated_pins()
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/openbmc/u-boot/arch/mips/mach-bmips/
H A DKconfig20 prompt "Broadcom MIPS SoC select"
134 Broadcom BCM968380GERG reference board with BCM68380 SoC with 512 MB
136 Between its different peripherals there's an integrated switch with 4
141 bool "Comtrend AR-5315u"
145 Comtrend AR-5315u boards have a BCM6318 SoC with 64 MB of RAM and 16
147 Between its different peripherals there's an integrated switch with 4
152 bool "Comtrend AR-5387un"
156 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
158 Between its different peripherals there's an integrated switch with 4
163 bool "Comtrend CT-5361"
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/openbmc/linux/arch/arm/mach-at91/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
18 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
34 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
45 Select this if you are using one of Microchip's SAMA5D3 family SoC.
59 Select this if you are using one of Microchip's SAMA5D4 family SoC.
70 Select this if you are using one of Microchip's SAMA7G5 family SoC.
73 bool "ARMv7 based Microchip LAN966 SoC family"
79 This enables support for ARMv7 based Microchip LAN966 SoC family.
93 Select this if you are using Microchip's AT91RM9200 SoC.
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/openbmc/linux/drivers/phy/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
29 Enable PCIe PHY support for Exynos SoC series.
33 tristate "Exynos SoC series UFS PHY driver"
37 Enable this to support the Samsung Exynos SoC UFS PHY driver for
42 tristate "S5P/Exynos SoC series USB 2.0 PHY driver"
51 2.0 PHY. Support for particular PHYs will be enabled based on the SoC
76 particular SoC is compiled in the driver. In case of S5PV210 two phys
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/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "pinctrl-mxs.h"
28 struct mxs_pinctrl_soc_data *soc; member
35 return d->soc->ngroups; in mxs_get_groups_count()
43 return d->soc->groups[group].name; in mxs_get_group_name()
51 *pins = d->soc->groups[group].pins; in mxs_get_group_pins()
52 *num_pins = d->soc->groups[group].npins; in mxs_get_group_pins()
57 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, in mxs_pin_dbg_show() argument
60 seq_printf(s, " %s", dev_name(pctldev->dev)); in mxs_pin_dbg_show()
72 int length = strlen(np->name) + SUFFIX_LEN; in mxs_dt_node_to_map()
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/openbmc/linux/drivers/memory/tegra/
H A Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
20 #include <soc/tegra/fuse.h>
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
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/openbmc/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
20 #include <soc/tegra/fuse.h>
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
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/openbmc/qemu/hw/dma/
H A Dsoc_dma.c2 * On-chip DMA controller framework.
21 #include "qemu/error-report.h"
27 memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); in transfer_mem2mem()
28 ch->paddr[0] += ch->bytes; in transfer_mem2mem()
29 ch->paddr[1] += ch->bytes; in transfer_mem2mem()
34 ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); in transfer_mem2fifo()
35 ch->paddr[0] += ch->bytes; in transfer_mem2fifo()
40 ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); in transfer_fifo2mem()
41 ch->paddr[1] += ch->bytes; in transfer_fifo2mem()
51 if (ch->bytes > fifo_size) in transfer_fifo2fifo()
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/openbmc/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2013
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include "../pinctrl-utils.h"
39 #include "pinctrl-abx500.h"
87 struct abx500_pinctrl_soc_data *soc; member
103 ret = abx500_get_register_interruptible(pct->dev, in abx500_gpio_get_bit()
106 dev_err(pct->dev, in abx500_gpio_get_bit()
107 "%s read reg =%x, offset=%x failed (%d)\n", in abx500_gpio_get_bit()
125 ret = abx500_mask_and_set_register_interruptible(pct->dev, in abx500_gpio_set_bits()
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/openbmc/linux/drivers/bus/
H A Dmvebu-mbus.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - One to configure the access of the CPU to the devices. Depending
17 * - One to configure the access to the CPU to the SDRAM. There are
23 * - Reads out the SDRAM address decoding windows at initialization
30 * devices have to configure those device -> SDRAM windows to ensure
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40 * see the list of CPU -> SDRAM windows and their configuration
41 * (file 'sdram') and the list of CPU -> devices windows and their
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/openbmc/linux/sound/soc/fsl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "SoC Audio for Freescale CPUs"
4 comment "Common SoC Audio options for Freescale CPUs:"
14 This option is only useful for out-of-tree drivers since
15 in-tree drivers select it automatically.
26 This option is only useful for out-of-tree drivers since
27 in-tree drivers select it automatically.
36 This option is only useful for out-of-tree drivers since
37 in-tree drivers select it automatically.
54 This option is only useful for out-of-tree drivers since
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/openbmc/u-boot/arch/mips/mach-ath79/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
14 const enum ath79_soc_type soc; member
51 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; in mach_cpu_init() local
91 soc = desc[i].soc; in mach_cpu_init()
96 gd->arch.id = id; in mach_cpu_init()
97 gd->arch.soc = soc; in mach_cpu_init()
98 gd->arch.rev = rev; in mach_cpu_init()
99 gd->arch.ver = ver; in mach_cpu_init()
105 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; in print_cpuinfo() local
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