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/openbmc/linux/kernel/rcu/
H A Dsrcutiny.c27 static int init_srcu_struct_fields(struct srcu_struct *ssp) in init_srcu_struct_fields() argument
29 ssp->srcu_lock_nesting[0] = 0; in init_srcu_struct_fields()
30 ssp->srcu_lock_nesting[1] = 0; in init_srcu_struct_fields()
31 init_swait_queue_head(&ssp->srcu_wq); in init_srcu_struct_fields()
32 ssp->srcu_cb_head = NULL; in init_srcu_struct_fields()
33 ssp->srcu_cb_tail = &ssp->srcu_cb_head; in init_srcu_struct_fields()
34 ssp->srcu_gp_running = false; in init_srcu_struct_fields()
35 ssp->srcu_gp_waiting = false; in init_srcu_struct_fields()
36 ssp->srcu_idx = 0; in init_srcu_struct_fields()
37 ssp->srcu_idx_max = 0; in init_srcu_struct_fields()
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H A Dsrcutree.c76 static void srcu_reschedule(struct srcu_struct *ssp, unsigned long delay);
122 static void init_srcu_struct_data(struct srcu_struct *ssp) in init_srcu_struct_data() argument
134 sdp = per_cpu_ptr(ssp->sda, cpu); in init_srcu_struct_data()
138 sdp->srcu_gp_seq_needed = ssp->srcu_sup->srcu_gp_seq; in init_srcu_struct_data()
139 sdp->srcu_gp_seq_needed_exp = ssp->srcu_sup->srcu_gp_seq; in init_srcu_struct_data()
144 sdp->ssp = ssp; in init_srcu_struct_data()
164 static bool init_srcu_struct_nodes(struct srcu_struct *ssp, gfp_t gfp_flags) in init_srcu_struct_nodes() argument
176 ssp->srcu_sup->node = kcalloc(rcu_num_nodes, sizeof(*ssp->srcu_sup->node), gfp_flags); in init_srcu_struct_nodes()
177 if (!ssp->srcu_sup->node) in init_srcu_struct_nodes()
181 ssp->srcu_sup->level[0] = &ssp->srcu_sup->node[0]; in init_srcu_struct_nodes()
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/openbmc/linux/drivers/tty/serial/
H A Dsifive.c218 * @ssp: pointer to a struct sifive_serial_port record
221 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
225 static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp) in __ssp_writel() argument
227 __ssp_early_writel(v, offs, &ssp->port); in __ssp_writel()
232 * @ssp: pointer to a struct sifive_serial_port record
236 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
242 static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs) in __ssp_readl() argument
244 return __ssp_early_readl(&ssp->port, offs); in __ssp_readl()
249 * @ssp: pointer to a struct sifive_serial_port
258 static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp) in sifive_serial_is_txfifo_full() argument
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/openbmc/linux/drivers/soc/pxa/
H A Dssp.c3 * linux/arch/arm/mach-pxa/ssp.c
5 * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
10 * PXA2xx SSP driver. This provides the generic core for simple
11 * IO-based SSP applications and allows easy port setup for DMA access.
40 struct ssp_device *ssp = NULL; in pxa_ssp_request() local
44 list_for_each_entry(ssp, &ssp_list, node) { in pxa_ssp_request()
45 if (ssp->port_id == port && ssp->use_count == 0) { in pxa_ssp_request()
46 ssp->use_count++; in pxa_ssp_request()
47 ssp->label = label; in pxa_ssp_request()
54 if (&ssp->node == &ssp_list) in pxa_ssp_request()
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/openbmc/linux/sound/soc/pxa/
H A Dpxa-ssp.c3 * pxa-ssp.c -- ALSA Soc Audio Layer
33 #include "pxa-ssp.h"
36 * SSP audio private data
39 struct ssp_device *ssp; member
53 static void dump_registers(struct ssp_device *ssp) in dump_registers() argument
55 dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", in dump_registers()
56 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), in dump_registers()
57 pxa_ssp_read_reg(ssp, SSTO)); in dump_registers()
59 dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", in dump_registers()
60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), in dump_registers()
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/openbmc/linux/include/linux/
H A Dsrcu.h28 int __init_srcu_struct(struct srcu_struct *ssp, const char *name,
31 #define init_srcu_struct(ssp) \ argument
35 __init_srcu_struct((ssp), #ssp, &__srcu_key); \
41 int init_srcu_struct(struct srcu_struct *ssp);
54 void call_srcu(struct srcu_struct *ssp, struct rcu_head *head,
56 void cleanup_srcu_struct(struct srcu_struct *ssp);
57 int __srcu_read_lock(struct srcu_struct *ssp) __acquires(ssp);
58 void __srcu_read_unlock(struct srcu_struct *ssp, int idx) __releases(ssp);
59 void synchronize_srcu(struct srcu_struct *ssp);
60 unsigned long get_state_synchronize_srcu(struct srcu_struct *ssp);
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H A Dpxa2xx_ssp.h5 * This driver supports the following PXA CPU/SSP ports:-
7 * PXA250 SSP
8 * PXA255 SSP, NSSP
9 * PXA26x SSP, NSSP, ASSP
29 * SSP Serial Port Registers
30 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
34 #define SSCR0 (0x00) /* SSP Control Register 0 */
35 #define SSCR1 (0x04) /* SSP Control Register 1 */
36 #define SSSR (0x08) /* SSP Status Register */
37 #define SSITR (0x0C) /* SSP Interrupt Test Register */
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H A Dsrcutiny.h55 void synchronize_srcu(struct srcu_struct *ssp);
63 static inline int __srcu_read_lock(struct srcu_struct *ssp) in __srcu_read_lock() argument
67 idx = ((READ_ONCE(ssp->srcu_idx) + 1) & 0x2) >> 1; in __srcu_read_lock()
68 WRITE_ONCE(ssp->srcu_lock_nesting[idx], READ_ONCE(ssp->srcu_lock_nesting[idx]) + 1); in __srcu_read_lock()
72 static inline void synchronize_srcu_expedited(struct srcu_struct *ssp) in synchronize_srcu_expedited() argument
74 synchronize_srcu(ssp); in synchronize_srcu_expedited()
77 static inline void srcu_barrier(struct srcu_struct *ssp) in srcu_barrier() argument
79 synchronize_srcu(ssp); in srcu_barrier()
83 static inline void srcu_torture_stats_print(struct srcu_struct *ssp, in srcu_torture_stats_print() argument
88 idx = ((data_race(READ_ONCE(ssp->srcu_idx)) + 1) & 0x2) >> 1; in srcu_torture_stats_print()
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/openbmc/linux/drivers/mmc/host/
H A Dmxs-mmc.c48 struct mxs_ssp ssp; member
64 struct mxs_ssp *ssp = &host->ssp; in mxs_mmc_get_cd() local
75 !(readl(ssp->base + HW_SSP_STATUS(ssp)) & in mxs_mmc_get_cd()
86 struct mxs_ssp *ssp = &host->ssp; in mxs_mmc_reset() local
90 ret = stmp_reset_block(ssp->base); in mxs_mmc_reset()
108 ssp->base + HW_SSP_TIMING(ssp)); in mxs_mmc_reset()
115 writel(ctrl0, ssp->base + HW_SSP_CTRL0); in mxs_mmc_reset()
116 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); in mxs_mmc_reset()
128 struct mxs_ssp *ssp = &host->ssp; in mxs_mmc_request_done() local
132 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); in mxs_mmc_request_done()
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/openbmc/linux/drivers/spi/
H A Dspi-mxs.c58 struct mxs_ssp ssp; member
67 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_setup_transfer() local
76 mxs_ssp_set_clk_rate(ssp, hz); in mxs_spi_setup_transfer()
79 * ssp->clk_rate. Otherwise we would set the rate every transfer in mxs_spi_setup_transfer()
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()
96 ssp->base + HW_SSP_CTRL1(ssp)); in mxs_spi_setup_transfer()
98 writel(0x0, ssp->base + HW_SSP_CMD0); in mxs_spi_setup_transfer()
99 writel(0x0, ssp->base + HW_SSP_CMD1); in mxs_spi_setup_transfer()
127 struct mxs_ssp *ssp = &spi->ssp; in mxs_ssp_wait() local
131 reg = readl_relaxed(ssp->base + offset); in mxs_ssp_wait()
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H A Dspi-pxa2xx-pci.c61 static int pxa2xx_spi_pci_clk_register(struct pci_dev *dev, struct ssp_device *ssp, in pxa2xx_spi_pci_clk_register() argument
66 snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); in pxa2xx_spi_pci_clk_register()
67 ssp->clk = clk_register_fixed_rate(&dev->dev, buf, NULL, 0, rate); in pxa2xx_spi_pci_clk_register()
68 if (IS_ERR(ssp->clk)) in pxa2xx_spi_pci_clk_register()
69 return PTR_ERR(ssp->clk); in pxa2xx_spi_pci_clk_register()
71 return devm_add_action_or_reset(&dev->dev, pxa2xx_spi_pci_clk_unregister, ssp->clk); in pxa2xx_spi_pci_clk_register()
92 struct ssp_device *ssp = &c->ssp; in lpss_spi_setup() local
99 ssp->type = LPSS_BYT_SSP; in lpss_spi_setup()
100 ssp->port_id = 0; in lpss_spi_setup()
105 ssp->type = LPSS_BSW_SSP; in lpss_spi_setup()
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H A Dspi-pxa2xx.c34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 * For testing SSCR1 changes that require SSP restart, basically
308 * Read and write LPSS SSP private registers. Caller must first check that
325 * lpss_ssp_setup - perform LPSS SSP specific setup
328 * Perform LPSS SSP specific setup. This function must be called first if
329 * one is going to use LPSS SSP private registers.
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; in lpss_ssp_setup()
449 /* Wait until SSP becomes idle before deasserting the CS */ in cs_deassert()
486 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_off()
625 dev_err(drv_data->ssp->dev, "%s\n", msg); in int_error_stop()
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/openbmc/linux/arch/arm/mach-sa1100/
H A Dssp.c3 * linux/arch/arm/mach-sa1100/ssp.c
7 * Generic SSP driver. This provides the generic core for simple
8 * IO-based SSP applications.
21 #include <asm/hardware/ssp.h>
30 printk(KERN_WARNING "SSP: receiver overrun\n"); in ssp_interrupt()
38 * ssp_write_word - write a word to the SSP port
41 * Wait for a free entry in the SSP transmit FIFO, and write a data
42 * word to the SSP port. Wait for the SSP port to start sending
74 * ssp_read_word - read a word from the SSP port
76 * Wait for a data word in the SSP receive FIFO, and return the
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmrvl,pxa-ssp.txt1 Device tree bindings for Marvell PXA SSP ports
6 mrvl,pxa25x-ssp
8 mrvl,pxa27x-ssp
9 mrvl,pxa3xx-ssp
10 mvrl,pxa168-ssp
11 mrvl,pxa910-ssp
12 mrvl,ce4100-ssp
21 ssp0: ssp@41000000 {
22 compatible = "mrvl,pxa3xx-ssp";
24 ssp-id = <1>;
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/openbmc/linux/drivers/input/mouse/
H A Dnavpoint.c3 * Synaptics NavPoint (PXA27x SSP/SPI) driver.
32 struct ssp_device *ssp; member
46 | SSCR0_SSE /* SSE = 1; SSP enabled */
120 struct ssp_device *ssp = navpoint->ssp; in navpoint_irq() local
124 status = pxa_ssp_read_reg(ssp, SSSR); in navpoint_irq()
128 pxa_ssp_write_reg(ssp, SSSR, (status & sssr)); in navpoint_irq()
135 data = pxa_ssp_read_reg(ssp, SSDR); in navpoint_irq()
143 status = pxa_ssp_read_reg(ssp, SSSR); in navpoint_irq()
152 struct ssp_device *ssp = navpoint->ssp; in navpoint_up() local
155 clk_prepare_enable(ssp->clk); in navpoint_up()
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/openbmc/linux/arch/x86/kernel/
H A Dshstk.c50 static int create_rstor_token(unsigned long ssp, unsigned long *token_addr) in create_rstor_token() argument
55 if (!IS_ALIGNED(ssp, 8)) in create_rstor_token()
58 addr = ssp - SS_FRAME_SIZE; in create_rstor_token()
61 * SSP is aligned, so reserved bits and mode bit are a zero, just mark in create_rstor_token()
64 ssp |= BIT(0); in create_rstor_token()
66 if (write_user_shstk_64((u64 __user *)addr, (u64)ssp)) in create_rstor_token()
79 * The shadow stack pointer(SSP) is moved by CALL, RET, and INCSSPQ. The
86 * and INCSSP. In addition to modifying SSP, INCSSP also reads from the
90 * READ_ONCE(ssp); // read+discard top element on stack
91 * ssp += nr_to_pop * 8; // move the shadow stack
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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dsys_proto.h41 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
42 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
45 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
46 { 0x09, 0x1f, "SSP SD/MMC #0" },
47 { 0x0a, 0x1f, "SSP SD/MMC #1" },
53 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
54 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
55 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
56 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
60 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
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/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h20 * SSP Serial Port Registers
24 u32 sscr0; /* SSP Control Register 0 - 0x000 */
25 u32 sscr1; /* SSP Control Register 1 - 0x004 */
26 u32 sssr; /* SSP Status Register - 0x008 */
27 u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
28 u32 ssdr; /* SSP Data Register - 0x010 */
30 u32 ssto; /* SSP Timeout Register - 0x028 */
31 u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
32 u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
33 u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt30 mpp10 10 gpio, pmu, ssp(sclk), pmu*
36 ssp(extclk), pmu*
37 mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
38 mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
47 uart1(cts), ssp(sfrm)
49 lcd-spi(mosi), uart1(cts), ssp(txd)
51 lcd-spi(sck), ssp(sclk)
55 mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
56 ssp/twsi
85 - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
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/openbmc/linux/drivers/clk/mxs/
H A Dclk-ssp.c21 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate) in mxs_ssp_set_clk_rate() argument
27 ssp_clk = clk_get_rate(ssp->clk); in mxs_ssp_set_clk_rate()
37 dev_err(ssp->dev, in mxs_ssp_set_clk_rate()
44 val = readl(ssp->base + HW_SSP_TIMING(ssp)); in mxs_ssp_set_clk_rate()
48 writel(val, ssp->base + HW_SSP_TIMING(ssp)); in mxs_ssp_set_clk_rate()
50 ssp->clk_rate = ssp_sck; in mxs_ssp_set_clk_rate()
52 dev_dbg(ssp->dev, in mxs_ssp_set_clk_rate()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmrvl,pxa-ssp.txt1 Marvell PXA SSP CPU DAI bindings
5 compatible Must be "mrvl,pxa-ssp-dai"
6 port A phandle reference to a PXA ssp upstream device
20 ssp1: ssp@41000000 {
21 compatible = "mrvl,pxa3xx-ssp";
24 clock-names = "pxa27x-ssp.0";
30 compatible = "mrvl,pxa-ssp-dai";
/openbmc/linux/Documentation/spi/
H A Dpxa2xx.rst2 PXA2xx SPI on SSP driver HOWTO
9 - Support for any PXA2xx and compatible SSP.
10 - SSP PIO and SSP DMA data transfers.
35 The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
67 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
107 used to configure the SSP hardware FIFO. These fields are critical to the
118 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
119 to determine the correct value. An SSP configured for byte-wide transfers would
124 trailing bytes in the SSP receiver FIFO. The correct value for this field is
126 slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
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/openbmc/linux/drivers/iio/common/ssp_sensors/
H A DKconfig3 # SSP sensor drivers and commons configuration
5 menu "SSP Sensor Common"
8 tristate "Commons for all SSP Sensor IIO drivers"
13 Say yes here to build commons for SSP sensors.
22 SSP driver for sensorhub.
23 If you say yes here you get ssp support for sensorhub.
/openbmc/linux/sound/soc/intel/catpt/
H A Dregisters.h35 #define CATPT_CS_SFCR(ssp) BIT(27 + (ssp)) argument
39 #define CATPT_CS_SDPM(ssp) BIT(11 + (ssp)) argument
44 #define CATPT_CS_SBCS(ssp) BIT(2 + (ssp)) argument
113 /* defaults to reset SSP registers to after each power cycle */
144 #define catpt_ssp_addr(cdev, ssp) \ argument
145 ((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp])
151 #define catpt_writel_ssp(cdev, ssp, reg, val) \ argument
152 writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
/openbmc/u-boot/board/spear/x600/
H A Dfpga.c20 * 16bit serial writes via this SSP port to write the data bits into the
77 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; in fpga_done_fn() local
82 while (!(readl(&ssp->sspsr) & SSPSR_TFE)) in fpga_done_fn()
126 * in SSP interface. So we don't have to do anything here. in fpga_clk_fn()
133 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; in fpga_wr_fn() local
156 while (!(readl(&ssp->sspsr) & SSPSR_TNF)) in fpga_wr_fn()
159 /* Send 16 bits to FPGA via SSP bus */ in fpga_wr_fn()
160 writel(data, &ssp->sspdr); in fpga_wr_fn()
230 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; in x600_init_fpga() local
244 writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); in x600_init_fpga()
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