Home
last modified time | relevance | path

Searched full:spe (Results 1 – 25 of 175) sorted by relevance

1234567

/openbmc/linux/tools/perf/util/
H A Darm-spe.c3 * Arm Statistical Profiling Extensions (SPE) support
33 #include "arm-spe.h"
34 #include "arm-spe-decoder/arm-spe-decoder.h"
35 #include "arm-spe-decoder/arm-spe-pkt-decoder.h"
84 struct arm_spe *spe; member
101 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, in arm_spe_dump()
111 ". ... ARM SPE data: size %#zx bytes\n", in arm_spe_dump()
140 static void arm_spe_dump_event(struct arm_spe *spe, unsigned char *buf, in arm_spe_dump_event() argument
144 arm_spe_dump(spe, buf, len); in arm_spe_dump_event()
154 queue = &speq->spe->queues.queue_array[speq->queue_nr]; in arm_spe_get_trace()
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A DMakefile8 obj-$(CONFIG_CRYPTO_AES_PPC_SPE) += aes-ppc-spe.o
11 obj-$(CONFIG_CRYPTO_SHA1_PPC_SPE) += sha1-ppc-spe.o
12 obj-$(CONFIG_CRYPTO_SHA256_PPC_SPE) += sha256-ppc-spe.o
20 aes-ppc-spe-y := aes-spe-core.o aes-spe-keys.o aes-tab-4k.o aes-spe-modes.o aes-spe-glue.o
23 sha1-ppc-spe-y := sha1-spe-asm.o sha1-spe-glue.o
24 sha256-ppc-spe-y := sha256-spe-asm.o sha256-spe-glue.o
H A DKconfig56 tristate "Hash functions: SHA-1 (SPE)"
57 depends on PPC && SPE
62 - SPE (Signal Processing Engine) extensions
65 tristate "Hash functions: SHA-224 and SHA-256 (SPE)"
66 depends on PPC && SPE
73 - SPE (Signal Processing Engine) extensions
76 tristate "Ciphers: AES, modes: ECB/CBC/CTR/XTS (SPE)"
77 depends on PPC && SPE
84 - SPE (Signal Processing Engine) extensions
86 SPE is available for:
H A Dsha256-spe-glue.c3 * Glue code for SHA-256 implementation for SPE instructions (PPC)
6 * about the SPE registers so it can run from interrupt context.
38 /* We just start SPE operations and will save SPE registers later. */ in spe_begin()
193 .cra_driver_name= "sha256-ppc-spe",
209 .cra_driver_name= "sha224-ppc-spe",
230 MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm, SPE optimized");
233 MODULE_ALIAS_CRYPTO("sha224-ppc-spe");
235 MODULE_ALIAS_CRYPTO("sha256-ppc-spe");
H A Dsha1-spe-glue.c3 * Glue code for SHA-1 implementation for SPE instructions (PPC)
37 /* We just start SPE operations and will save SPE registers later. */ in spe_begin()
167 .cra_driver_name= "sha1-ppc-spe",
188 MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, SPE optimized");
191 MODULE_ALIAS_CRYPTO("sha1-ppc-spe");
H A Daes-spe-glue.c3 * Glue code for AES implementation for SPE instructions (PPC)
6 * about the SPE registers so it can run from interrupt context.
80 /* disable preemption and save users SPE registers if required */ in spe_begin()
415 .cra_driver_name = "aes-ppc-spe",
436 .base.cra_driver_name = "ecb-ppc-spe",
448 .base.cra_driver_name = "cbc-ppc-spe",
461 .base.cra_driver_name = "ctr-ppc-spe",
475 .base.cra_driver_name = "xts-ppc-spe",
515 MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS, SPE optimized");
522 MODULE_ALIAS_CRYPTO("aes-ppc-spe");
/openbmc/openbmc/poky/meta/conf/machine/include/powerpc/
H A Dtune-ppce500.inc8 TUNEVALID[spe] = "Enable SPE ABI extensions"
9 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', [ 'ppce500', 'spe' ], ' -mabi=spe -mspe -mflo…
10 TARGET_FPU .= "${@bb.utils.contains('TUNE_FEATURES', [ 'ppce500' , 'spe' ], 'ppc-efs', '', d)}"
12 # spe is defined potentially in two places, so we want to be sure it will
13 # only write spe once to the ABIEXTENSIONS field.
14 SPEABIEXTENSION = "${@bb.utils.filter('TUNE_FEATURES', 'spe', d)}"
18 TUNE_FEATURES:tune-ppce500 = "m32 spe ppce500 bigendian"
H A Dtune-ppce500v2.inc8 TUNEVALID[spe] = "Enable SPE ABI extensions"
9 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', [ 'ppce500v2', 'spe' ], ' -mabi=spe -mspe -mf…
10 TARGET_FPU .= "${@bb.utils.contains('TUNE_FEATURES', [ 'ppce500v2' , 'spe' ], 'ppc-efd', '', d)}"
12 # spe is defined potentially in two places, so we want to be sure it will
13 # only write spe once to the ABIEXTENSIONS field.
14 SPEABIEXTENSION = "${@bb.utils.filter('TUNE_FEATURES', 'spe', d)}"
/openbmc/openbmc/poky/meta/recipes-devtools/gcc/gcc/
H A D0019-Re-introduce-spe-commandline-options.patch4 Subject: [PATCH] Re-introduce spe commandline options
7 spe options
9 Upstream-Status: Inappropriate [SPE port is removed from rs600 port]
24 +; PPC SPE ABI
27 +Generate SPE SIMD instructions on E500.
29 +mabi=spe
31 +Use the SPE ABI extensions.
33 +mabi=no-spe
35 +Do not use the SPE ABI extensions.
/openbmc/linux/tools/perf/Documentation/
H A Dperf-arm-spe.txt1 perf-arm-spe(1)
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
16 The SPE (Statistical Profiling Extension) feature provides accurate attribution of latencies and
32 This is chosen from a sample population, for SPE this is an IMPLEMENTATION DEFINED choice of all
34 architecture provides a mechanism for the SPE driver to infer the minimum interval at which it shou…
64 Up until this point no decoding of the SPE data was done by either the kernel or Perf. Only when the
67 recording. These samples are the same as if normal sampling was done by Perf without using SPE,
69 just the instruction pointer, but an SPE sample can have data addresses and latency attributes.
84 However, SPE does not provide any call-graph information, and relies on statistical methods.
119 Capturing SPE with perf command-line tools
[all …]
H A Dperf-mem.txt26 On Arm64 this uses SPE to sample load and store operations, therefore hardware
27 and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.
28 Due to the statistical nature of SPE sampling, not every memory operation will
101 linkperf:perf-record[1], linkperf:perf-report[1], linkperf:perf-arm-spe[1]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dicon.dts33 model = "PowerPC,440SPe";
53 compatible = "ibm,uic-440spe","ibm,uic";
63 compatible = "ibm,uic-440spe","ibm,uic";
75 compatible = "ibm,uic-440spe","ibm,uic";
87 compatible = "ibm,uic-440spe","ibm,uic";
99 compatible = "ibm,sdr-440spe";
104 compatible = "ibm,cpr-440spe";
109 compatible = "ibm,mq-440spe";
114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
[all …]
H A Dkatmai.dts37 model = "PowerPC,440SPe";
57 compatible = "ibm,uic-440spe","ibm,uic";
67 compatible = "ibm,uic-440spe","ibm,uic";
79 compatible = "ibm,uic-440spe","ibm,uic";
91 compatible = "ibm,uic-440spe","ibm,uic";
103 compatible = "ibm,sdr-440spe";
108 compatible = "ibm,cpr-440spe";
113 compatible = "ibm,mq-440spe";
118 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
135 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
[all …]
/openbmc/linux/tools/perf/tests/shell/
H A Dtest_arm_spe.sh2 # Check Arm SPE trace data recording and synthesized samples
4 # Uses the 'perf record' to record trace data of Arm SPE events;
5 # then verify if any SPE event samples are generated by SPE with
46 # from arm-spe.c/arm_spe_synth_events()
88 arm_spe_report "SPE snapshot testing" $err
96 arm_spe_report "SPE system-wide testing" 2
107 arm_spe_report "SPE system-wide testing" $err
H A Dtest_arm_spe_fork.sh2 # Check Arm SPE doesn't hang when there are forks
44 echo "SPE hang test: FAIL"
47 echo "SPE hang test: PASS"
/openbmc/linux/arch/powerpc/platforms/cell/
H A Dspu_manage.c37 static u64 __init find_spu_unit_number(struct device_node *spe) in find_spu_unit_number() argument
43 prop = of_get_property(spe, "physical-id", &proplen); in find_spu_unit_number()
48 prop = of_get_property(spe, "unit-id", &proplen); in find_spu_unit_number()
53 prop = of_get_property(spe, "reg", &proplen); in find_spu_unit_number()
261 pr_debug("failed to map spe %s: %d\n", spu->name, ret); in spu_map_device()
272 for_each_node_by_type(node, "spe") { in of_enumerate_spus()
288 struct device_node *spe = (struct device_node *)data; in of_create_spu() local
291 spu->devnode = of_node_get(spe); in of_create_spu()
292 spu->spe_id = find_spu_unit_number(spe); in of_create_spu()
294 spu->node = of_node_to_nid(spe); in of_create_spu()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Dspe-pmu.yaml4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
37 spe-pmu {
/openbmc/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dppc440spe-adma.txt15 - compatible : "ibm,i2o-440spe";
22 compatible = "ibm,i2o-440spe";
32 - compatible : "ibm,dma-440spe";
45 compatible = "ibm,dma-440spe";
82 - compatible : "ibm,mq-440spe";
88 compatible = "ibm,mq-440spe";
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dconfig.mk9 # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
10 # see "[PATCH,rs6000] make -mno-spe work as expected" on
13 $(call cc-option,-mno-spe)
/openbmc/linux/arch/powerpc/platforms/ps3/
H A Dspu.c28 * enum spe_type - Type of spe to create.
29 * @spe_type_logical: Standard logical spe.
40 * struct spe_shadow - logical spe shadow register area.
42 * Read-only shadow of spe registers.
66 * enum spe_ex_state - Logical spe execution state.
71 * The execution state (status) of the logical spe as reported in
83 * @masks[]: Array of cached spe interrupt masks, indexed by class.
96 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
97 * @resource_id: HV spe resource id returned by
99 * @priv2_addr: lpar address of spe priv2 area returned by
[all …]
/openbmc/linux/tools/perf/arch/arm64/util/
H A Dmem-events.c8 …E("spe-load", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "a…
9 E("spe-store", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"),
10 …E("spe-ldst", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "a…
/openbmc/linux/arch/powerpc/include/asm/
H A Ddcr-regs.h28 /* CPRs (440GX and 440SP/440SPe) */
32 /* SDRs (440GX and 440SP/440SPe) */
162 * DCR register offsets for 440SP/440SPe I2O/DMA controller.
169 /* 440SP/440SPe Software Reset DCR */
173 /* 440SP/440SPe Memory Queue DCR offsets */
/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype412 config SPE config
413 bool "SPE Support"
418 Extensions (SPE) to the PowerPC processor. The kernel currently
419 supports saving and restoring SPE registers, and turning on the
420 'spe enable' bit so user processes can execute SPE instructions.
423 SPE (e500, otherwise known as 85xx series), but does not have any
424 effect on a non-spe cpu (it does, however add code to the kernel).
/openbmc/linux/tools/perf/util/arm-spe-decoder/
H A DBuild1 perf-$(CONFIG_AUXTRACE) += arm-spe-pkt-decoder.o arm-spe-decoder.o
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A De500v2_power_isa.dtsi47 power-isa-sp.fd; // SPE.Embedded Float Scalar Double
48 power-isa-sp.fs; // SPE.Embedded Float Scalar Single
49 power-isa-sp.fv; // SPE.Embedded Float Vector

1234567