| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 33 qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
41 -machine virt,kernel_irqchip=on,iommu=smmuv3,default_bus_bypass_iommu=true \
46 - a default host bridge which bypass SMMUv3
47 - a pxb host bridge which go through SMMUv3
48 - a pxb host bridge which bypass SMMUv3
77 - Arm SMMUv3 support
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| /openbmc/qemu/hw/arm/ |
| H A D | smmuv3.c | 33 #include "hw/arm/smmuv3.h"
34 #include "smmuv3-internal.h"
391 * In architectures after SMMUv3.0:
436 "SMMUv3 AArch32 tables not supported\n"); in decode_ste_s2_cfg()
452 "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste)); in decode_ste_s2_cfg()
461 qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 = 0x3 has no meaning!\n"); in decode_ste_s2_cfg()
468 * For SMMUv3.1 and later, when OAS == IAS == 52, the stage 2 input in decode_ste_s2_cfg()
481 "SMMUv3 S2TTB too large 0x%" PRIx64 in decode_ste_s2_cfg()
490 qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ = %d\n", in decode_ste_s2_cfg()
498 "SMMUv3 STE stage 2 config not valid!\n"); in decode_ste_s2_cfg()
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| H A D | virt-acpi-build.c | 236 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
319 nb_nodes = 3; /* RC, ITS, SMMUv3 */ in build_iort()
348 /* Table 9 SMMUv3 Format */ in build_iort()
349 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ in build_iort()
410 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ in build_iort()
413 /* output IORT node is the smmuv3 node */ in build_iort()
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| H A D | meson.build | 56 arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
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| H A D | trace-events | 23 # smmuv3.c
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| H A D | virt.c | 75 #include "hw/arm/smmuv3.h"
1441 node = g_strdup_printf("/smmuv3@%" PRIx64, base); in create_smmu()
2724 return g_strdup("smmuv3"); in virt_get_iommu()
2734 if (!strcmp(value, "smmuv3")) { in virt_set_iommu()
2740 error_append_hint(errp, "Valid values are none, smmuv3.\n"); in virt_set_iommu()
3218 "Valid values are none and smmuv3"); in virt_machine_class_init()
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| H A D | smmuv3-internal.h | 2 * ARM SMMUv3 support - Internal API
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | arm,smmu-v3-pmcg.yaml | 7 title: Arm SMMUv3 Performance Monitor Counter Group
14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
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| /openbmc/qemu/include/hw/arm/ |
| H A D | smmuv3.h | 25 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
84 #define TYPE_ARM_SMMUV3 "arm-smmuv3"
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | arm,smmu-v3.yaml | 7 title: ARM SMMUv3 Architecture Implementation
14 The SMMUv3 architecture is a significant departure from previous
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| /openbmc/linux/drivers/iommu/ |
| H A D | Kconfig | 391 tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support"
401 the ARM SMMUv3 architecture.
404 bool "Shared Virtual Addressing support for the ARM SMMUv3"
410 SMMUv3.
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| /openbmc/qemu/tests/avocado/ |
| H A D | smmu.py | 1 # SMMUv3 Functional tests
48 self.vm.add_args("-machine", "iommu=smmuv3")
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| /openbmc/qemu/docs/system/arm/ |
| H A D | virt.rst | 33 - An optional SMMUv3 IOMMU
167 ``smmuv3``
168 Create an SMMUv3
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| /openbmc/linux/drivers/perf/ |
| H A D | Kconfig | 94 tristate "ARM SMMUv3 Performance Monitors Extension"
98 Provides support for the ARM SMMUv3 Performance Monitor Counter
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| H A D | arm_smmuv3_pmu.c | 5 * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
8 * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
774 flags, "smmuv3-pmu", pmu); in smmu_pmu_setup_irq()
1035 MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
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| /openbmc/linux/include/linux/ |
| H A D | acpi_iort.h | 22 #define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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| /openbmc/linux/drivers/acpi/arm64/ |
| H A D | iort.c | 418 * SMMUv3 dev ID mapping index was introduced in revision 1 in iort_get_id_mapping_index()
1457 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_count_resources()
1479 * irq line. Use single irq line for all the SMMUv3 interrupts. in arm_smmu_v3_is_combined_irq()
1511 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_init_resources()
1555 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_dma_configure()
1561 /* We expect the dma masks to be equivalent for all SMMUv3 set-ups */ in arm_smmu_v3_dma_configure()
1570 * set numa proximity domain for smmuv3 device
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| /openbmc/qemu/tests/functional/ |
| H A D | test_aarch64_virt.py | 55 "gic-version=max,iommu=smmuv3")
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| /openbmc/qemu/docs/devel/migration/ |
| H A D | uadk-compression.rst | 137 directly it is possible that SMMUv3 may encounter page faults while walking the
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| /openbmc/linux/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3.h | 3 * IOMMU API for ARM architected SMMUv3 implementations.
623 /* An SMMUv3 instance */
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| H A D | arm-smmu-v3-sva.c | 3 * Implementation of the IOMMU SVA API for the ARM SMMUv3
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| H A D | arm-smmu-v3.c | 3 * IOMMU API for ARM architected SMMUv3 implementations.
3262 * lines. Use a single irq line for all the SMMUv3 interrupts. in arm_smmu_setup_irqs()
3714 /* Retrieve SMMUv3 specific data */ in arm_smmu_device_acpi_probe()
3950 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip06.dtsi | 328 * of HiSilicon platforms hip06/hip07 to support the SMMUv3
334 * ARM SMMUv3 driver requires a quirk to treat the MSI regions
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| /openbmc/linux/include/acpi/ |
| H A D | actbl2.h | 526 u64 base_address; /* SMMUv3 base address */
541 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */
542 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* hi_silicon Hi161x SMMUv3 */
543 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | silicon-errata.rst | 219 | Cavium | ThunderX2 SMMUv3| #74 | N/A |
221 | Cavium | ThunderX2 SMMUv3| #126 | N/A |
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