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/openbmc/linux/arch/arm/mach-zynq/
H A Dslcr.c3 * Xilinx SLCR driver
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
49 * @val: Pointer to value to be read from SLCR
50 * @offset: Register offset in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
189 * zynq_early_slcr_init - Early slcr init function
193 * Called very early during boot from platform code to unlock SLCR.
199 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
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H A DMakefile7 obj-y := common.o slcr.o pm.o
H A Dplatsmp.c36 /* MS: Expectation that SLCR are directly map and accessible */ in zynq_cpun_start()
/openbmc/linux/drivers/reset/
H A Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
101 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c27 /* Offsets into SLCR regmap */
110 /* Masks for controlling stuff in SLCR */
127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
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/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c81 * of the SLCR block. Clobbers r1.
208 DeviceState *dev, *slcr; in zynq_init() local
250 /* Create the main clock source, and feed slcr with it */ in zynq_init()
257 /* Create slcr, keep a pointer to connect clocks */ in zynq_init()
258 slcr = qdev_new("xilinx-zynq_slcr"); in zynq_init()
259 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); in zynq_init()
260 qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); in zynq_init()
261 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); in zynq_init()
262 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); in zynq_init()
295 qdev_get_clock_out(slcr, "uart0_ref_clk")); in zynq_init()
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H A Dxlnx-versal.c355 * - PMC SLCR in versal_create_pmc_apb_irq_orgate()
497 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, in versal_create_pmc_iou_slcr()
500 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); in versal_create_pmc_iou_slcr()
579 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, in versal_create_ospi()
876 "PMC SLCR parity interrupt behaviour " in versal_unimp_irq_parity_imr()
905 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, in versal_unimp()
909 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, in versal_unimp()
913 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
918 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cse-nand.dts41 slcr: slcr@f8000000 { label
45 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-cse-nor.dts50 slcr: slcr@f8000000 { label
53 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-cse-qspi.dtsi93 slcr: slcr@f8000000 { label
97 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-7000.dtsi258 slcr: slcr@f8000000 { label
262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
288 syscon = <&slcr>;
294 syscon = <&slcr>;
323 syscon = <&slcr>;
/openbmc/u-boot/doc/
H A DREADME.zynq36 Zynq has a facility to read the bootmode from the slcr bootmode register
42 board_late_init() will read the bootmode values using slcr bootmode register
46 SLCR bootmode register Bit[3:0] values
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml32 Phandle to syscon block which provide access to SLCR registers
51 syscon = <&slcr>;
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,zynq-pinctrl.yaml34 description: Specifies the base address and size of the SLCR space.
39 phandle to the SLCR.
186 syscon = <&slcr>;
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi310 slcr: slcr@f8000000 { label
313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
338 syscon = <&slcr>;
344 syscon = <&slcr>;
373 syscon = <&slcr>;
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h2 * Header file for the Xilinx Versal's PMC IOU SLCR
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
/openbmc/linux/drivers/clk/zynq/
H A Dclkc.c580 struct device_node *slcr; in zynq_clock_init() local
594 slcr = of_get_parent(np); in zynq_clock_init()
596 if (slcr->data) { in zynq_clock_init()
597 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
600 of_node_put(slcr); in zynq_clock_init()
606 of_node_put(slcr); in zynq_clock_init()
/openbmc/u-boot/arch/arm/mach-zynq/
H A DMakefile12 obj-y += slcr.o
H A Dslcr.c109 * Unlock the SLCR then reset the system. in zynq_slcr_cpu_reset()
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h32 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
109 XlnxVersalPmcIouSlcr slcr; member
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst18 - Zynq SLCR
/openbmc/linux/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c121 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
315 * CPM SLCR block. in xilinx_cpm_pcie_event_flow()
508 * CPM SLCR block. in xilinx_cpm_pcie_init_port()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
/openbmc/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h29 /* Reflect slcr offsets */

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