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/openbmc/u-boot/doc/device-tree-bindings/reset/
H A Dreset.txt1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
[all …]
H A Dti,sci-reset.txt1 Texas Instruments TI SCI Reset Controller
11 Reset Controller Node
13 The reset controller node represents the resets of various hardware modules
19 - compatible: Must be "ti,sci-reset"
20 - #reset-cells: Must be 2. Please see the reset consumer node below for
28 k3_reset: reset-controller {
29 compatible = "ti,sci-reset";
30 #reset-cells = <2>;
34 Reset Consumers
36 Each of the reset consumer nodes should have the following properties,
[all …]
/openbmc/u-boot/drivers/reset/
H A DKconfig1 menu "Reset Controller Support"
4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable the sandbox reset test driver"
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
[all …]
H A DMakefile6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
8 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
11 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
12 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
14 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
15 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
[all …]
H A Dreset-ti-sci.c3 * Texas Instruments System Control Interface (TI SCI) reset driver
8 * Loosely based on Linux kernel reset-ti-sci.c...
14 #include <reset-uclass.h>
18 * struct ti_sci_reset_data - reset controller information structure
53 * On TI SCI-based devices, the reset provider id field is used as a in ti_sci_reset_of_xlate()
54 * device ID, and the data field is used as the associated reset mask. in ti_sci_reset_of_xlate()
75 * ti_sci_reset_set() - program a device's reset
76 * @rst: Handle to a single reset signal
80 * reset using the TI SCI protocol. The device's reset is asserted if the
83 * reset register is read using a TI SCI device operation, the new value is
[all …]
/openbmc/u-boot/include/
H A Dreset.h12 * A reset is a hardware signal indicating that a HW module (or IP block, or
13 * sometimes an entire off-CPU chip) reset all of its internal state to some
14 * known-good initial state. Drivers will often reset HW modules when they
16 * or in response to some error condition. Reset signals are often controlled
17 * externally to the HW module being reset, by an entity this API calls a reset
19 * reset controllers set or clear reset signals.
21 * A driver that implements UCLASS_RESET is a reset controller or provider. A
22 * controller will often implement multiple separate reset signals, since the
23 * hardware it manages often has this capability. reset-uclass.h describes the
24 * interface which reset controllers must implement.
[all …]
H A Dsysreset.h11 SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
12 SYSRESET_COLD, /* Reset CPU and GPIOs */
13 SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
23 * Note that this function may return before the reset takes effect.
25 * @type: Reset type to request
26 * @return -EINPROGRESS if the reset has been started and
28 * by this device, 0 if the reset has already happened
33 * get_status() - get printable reset status information
36 * @buf: Buffer to receive the textual reset information
43 * get_last() - get information on the last reset
[all …]
H A Dreset-uclass.h9 /* See reset.h for background documentation. */
11 #include <reset.h>
17 * struct reset_ops - The functions that a reset controller driver must
22 * of_xlate - Translate a client's device-tree (OF) reset specifier.
24 * The reset core calls this function as the first step in implementing
27 * If this function pointer is set to NULL, the reset core will use a
28 * default implementation, which assumes #reset-cells = <1>, and that
29 * the DT cell contains a simple integer reset signal ID.
31 * At present, the reset API solely supports device-tree. If this
35 * @reset_ctl: The reset control struct to hold the translation result.
[all …]
/openbmc/u-boot/drivers/sysreset/
H A DKconfig2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
12 board. Each driver can provide a reset method which will be called
13 to effect a reset. The uclass will try all available drivers when
19 bool "Enable support for GPIO reset driver"
22 Reset support via GPIO pin connected reset logic. This is used for
23 example on Microblaze where reset logic can be controlled via GPIO
24 pin which triggers cpu reset.
[all …]
/openbmc/qemu/docs/devel/
H A Dreset.rst3 Reset in QEMU: the Resettable interface
6 The reset of qemu objects is handled using the resettable interface declared
10 whole group can be reset consistently. Each individual member object does not
12 reset first) are addressed.
17 Triggering reset
24 You can apply a reset to an object using ``resettable_assert_reset()``. You need
25 to call ``resettable_release_reset()`` to release the object from reset. To
26 instantly reset an object, without keeping it in reset state, just call
28 object to reset and a reset type.
30 The Resettable interface handles reset types with an enum ``ResetType``:
[all …]
/openbmc/openbmc-test-automation/data/boot_lists/
H A DOBMC_reboot19 IPMI MC Reset Warm (run)
20 IPMI MC Reset Warm (run) (mfg)
21 IPMI MC Reset Warm (off)
22 IPMI MC Reset Warm (off) (mfg)
23 IPMI MC Reset Cold (off)
24 IPMI MC Reset Cold (off) (mfg)
25 IPMI MC Reset Cold (run)
26 IPMI MC Reset Cold (run) (mfg)
27 IPMI Std MC Reset Warm (off)
28 IPMI Std MC Reset Warm (off) (mfg)
[all …]
H A DAll41 IPMI MC Reset Warm (run)
42 IPMI MC Reset Warm (run) (mfg)
43 IPMI MC Reset Warm (off)
44 IPMI MC Reset Warm (off) (mfg)
45 IPMI MC Reset Cold (off)
46 IPMI MC Reset Cold (off) (mfg)
47 IPMI MC Reset Cold (run)
48 IPMI MC Reset Cold (run) (mfg)
49 IPMI Std MC Reset Warm (off)
50 IPMI Std MC Reset Warm (off) (mfg)
[all …]
/openbmc/u-boot/drivers/reset/aspeed/
H A DKconfig2 bool "Reset controller driver for ASPEED AST2400 SoCs"
6 Support for reset controller on ASPEED SoC. This controller uses
7 watchdog to reset different peripherals and thus only supports
9 is that some reset signals, like I2C or MISC reset multiple devices.
12 bool "Reset controller driver for ASPEED AST2500 SoCs"
16 Support for reset controller on ASPEED SoC. This controller uses
17 watchdog to reset different peripherals and thus only supports
19 is that some reset signals, like I2C or MISC reset multiple devices.
22 bool "Reset controller driver for ASPEED AST2600 SoCs"
26 Support for reset controller on ASPEED SoC. This controller uses
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
56 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_r40.c13 #include <dt-bindings/reset/sun8i-r40-ccu.h>
57 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
58 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
59 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
61 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
62 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
63 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
64 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
65 [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)),
66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[all …]
H A Dclk_h3.c13 #include <dt-bindings/reset/sun8i-h3-ccu.h>
53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
56 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
58 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
59 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
60 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
61 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[all …]
H A Dclk_a31.c13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
58 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
59 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
60 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
61 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
[all …]
H A Dclk_a64.c13 #include <dt-bindings/reset/sun50i-a64-ccu.h>
46 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
47 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
48 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
50 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
51 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
52 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
53 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
54 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
55 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-crl.c2 * QEMU model of the Clock-Reset-LPD (CRL).
101 /* A single register fans out to all ADMA reset inputs. */ in crl_rst_adma_prew()
103 REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); in crl_rst_adma_prew()
112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); in crl_rst_uart0_prew()
120 REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); in crl_rst_uart1_prew()
128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); in crl_rst_gem1_prew()
144 REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); in crl_rst_usb_prew()
154 .reset = 0x1,
162 .reset = 0x1,
[all …]
/openbmc/qemu/include/system/
H A Dreset.h2 * Reset handlers.
36 * qemu_register_resettable: Register an object to be reset
37 * @obj: object to be reset: it must implement the Resettable interface
39 * Register @obj on the list of objects which will be reset when the
40 * simulation is reset. These objects will be reset in the order
46 * It is not permitted to register or unregister reset functions or
47 * resettable objects from within any of the reset phase methods of @obj.
54 * qemu_unregister_resettable: Unregister an object to be reset
57 * Remove @obj from the list of objects which are reset when the
58 * simulation is reset. It must have been previously added to
[all …]
/openbmc/openbmc-test-automation/gui/gui_test/settings_menu/
H A Dtest_factory_reset_sub_menu.robot3 Documentation Test suite for OpenBMC GUI "Factory reset" sub-menu of "Settings" menu.
14 ${xpath_factory_reset_heading} //h1[text()="Factory reset"]
15 ${xpath_reset_button} //button[contains(text(),'Reset')]
22 Verify Navigation To Factory Reset Page
23 [Documentation] Verify navigation to factory reset page.
29 Verify Existence Of All Sections In Factory Reset Page
30 [Documentation] Verify existence of all sections in factory reset page.
33 Page Should Contain Reset options
36 Verify Existence Of All Buttons In Factory Reset Page
37 [Documentation] Verify existence of all buttons in factory reset page.
[all …]
/openbmc/openbmc-test-automation/docs/
H A Dboot_test.md56 IPMI MC Reset Warm (run) 0 0 0
57 IPMI MC Reset Warm (run) (mfg) 0 0 0
58 IPMI MC Reset Warm (off) 0 0 0
59 IPMI MC Reset Warm (off) (mfg) 0 0 0
60 IPMI MC Reset Cold (run) 0 0 0
61 IPMI MC Reset Cold (run) (mfg) 0 0 0
62 IPMI MC Reset Cold (off) 0 0 0
63 IPMI MC Reset Cold (off) (mfg) 0 0 0
64 IPMI Std MC Reset Warm (run) 0 0 0
65 IPMI Std MC Reset Warm (run) (mfg) 0 0 0
[all …]
/openbmc/qemu/include/hw/
H A Dresettable.h29 * Types of reset.
31 * + Cold: reset resulting from a power cycle of the object.
32 * + Wakeup: reset resulting from a wake-up from a suspended state.
49 * See docs/devel/reset.rst for more detailed information about how QEMU models
50 * reset. This whole API must only be used when holding the iothread mutex.
52 * All objects which can be reset must implement this interface;
55 * progress of a reset operation by providing a ResettableState structure.
57 * state of the reset.
67 * for any reset event, in the order 'enter', 'hold', 'exit'.
70 * before eventually reset is deasserted and the 'exit' phase is called.
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c159 static uint32_t reset(uint32_t gpio, unsigned int offset) in reset() function
176 * after reset are correct, and that the value in IDR is in test_idr_reset_value()
178 * Since AF and analog modes aren't implemented, IDR reset in test_idr_reset_value()
218 g_assert_cmphex(moder, ==, reset(GPIO_A, MODER)); in test_idr_reset_value()
219 g_assert_cmphex(odr, ==, reset(GPIO_A, ODR)); in test_idr_reset_value()
220 g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER)); in test_idr_reset_value()
222 g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR)); in test_idr_reset_value()
223 /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */ in test_idr_reset_value()
224 g_assert_cmphex(idr, ==, reset(GPIO_A, IDR)); in test_idr_reset_value()
233 g_assert_cmphex(moder, ==, reset(GPIO_B, MODER)); in test_idr_reset_value()
[all …]
/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_resets.robot2 Documentation Module to test IPMI cold and warm reset functionalities.
21 Test IPMI Warm Reset
22 [Documentation] Check IPMI warm reset and wait for BMC to become online.
24 Repeat Keyword ${LOOP_COUNT} times IPMI MC Reset Warm (off)
27 Test IPMI Cold Reset
28 [Documentation] Check IPMI cold reset and wait for BMC to become online.
31 Repeat Keyword ${LOOP_COUNT} times IPMI MC Reset Cold (run)
41 Verify Power Reset via IPMI
42 [Documentation] Verify IPMI power reset command works fine.
45 Repeat Keyword ${LOOP_COUNT} times IPMI Power Reset

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