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/openbmc/linux/arch/arm64/kernel/
H A Dsleep.S14 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
32 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
42 lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
/openbmc/linux/arch/arm/kernel/
H A Dsleep.S15 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
33 * Input registers: rs0, rs1, rs2, mpidr, mask
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
41 ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
42 THUMB( lsr \dst, \dst, \rs0 )
/openbmc/qemu/target/mips/tcg/
H A Ddsp_helper.c1256 uint8_t rs3, rs2, rs1, rs0; \
1260 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1266 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1429 uint8_t rs6, rs4, rs2, rs0; in helper_precr_ob_qh() local
1436 rs0 = rs & MIPSDSP_Q0; in helper_precr_ob_qh()
1443 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) | in helper_precr_ob_qh()
1452 * In case sa == 0, use rt2, rt0, rs2, rs0.
1460 uint16_t rs3, rs2, rs1, rs0; \
1464 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1471 tempA = rs0 << var; \
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/openbmc/linux/include/linux/rtc/
H A Dds1685.h154 #define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
291 * Periodic rates are selected by setting the RS3-RS0 bits in Control
295 * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
311 /* E32K RS3 RS2 RS1 RS0 */
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsff,sfp.yaml60 GPIO phandle and a specifier of the Rx Signaling Rate Select (AKA RS0)
/openbmc/linux/drivers/edac/
H A Dpnd2_edac.h223 u32 rs0 : 5; member
H A Dpnd2_edac.c978 daddr->rank = dnv_get_bit(pmiaddr, dmap[pmiidx].rs0 + 13, 0); in dnv_pmi2mem()
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7724.c285 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
/openbmc/qemu/hw/sensor/
H A Dmax34451.c70 | 0 | Power supply monitored by RS0, controlled by PSEN0, and |
/openbmc/linux/drivers/net/phy/
H A Dsfp.c1689 seq_printf(s, "rs0: %d\n", !!(sfp->state & SFP_F_RS0)); in sfp_debug_state_show()
2012 * SFF-8079 reveals that it is understood that RS0 will be low for in sfp_module_parse_rate_select()
2048 * Channel 1.0625/2.125/4.25 Gbd modes. Note that RS0 in sfp_module_parse_rate_select()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h1411 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
1412 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_common.c4359 /* Set RS0 */ in ixgbe_set_soft_rate_select_speed()
4364 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4374 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
H A Dixgbe_82599.c628 * Set module link speed via RS0/RS1 rate select pins.
/openbmc/linux/drivers/rtc/
H A Drtc-ds1685.c1146 /* Clear RS3-RS0 in Control A. */ in ds1685_rtc_probe()