| /openbmc/linux/drivers/media/pci/bt8xx/ |
| H A D | btcx-risc.c | 4 btcx-risc.c
6 bt848/bt878/cx2388x risc code generator.
23 #include "btcx-risc.h"
37 /* allocate/free risc memory */
42 struct btcx_riscmem *risc) in btcx_riscmem_free() argument
44 if (NULL == risc->cpu) in btcx_riscmem_free()
49 memcnt, (unsigned long)risc->dma); in btcx_riscmem_free()
51 dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma); in btcx_riscmem_free()
52 memset(risc,0,sizeof(*risc)); in btcx_riscmem_free()
56 struct btcx_riscmem *risc, in btcx_riscmem_alloc() argument
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| H A D | bttv-risc.c | 4 bttv-risc.c -- interfaces to other kernel modules
6 bttv risc code handling
32 /* risc code generators */
35 bttv_risc_packed(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_packed() argument
46 /* estimate risc mem: worst case is one write per page border + in bttv_risc_packed()
54 if ((rc = btcx_riscmem_alloc(btv->c.pci,risc,instructions)) < 0) in bttv_risc_packed()
58 rp = risc->cpu; in bttv_risc_packed()
108 risc->jmp = rp; in bttv_risc_packed()
109 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in bttv_risc_packed()
114 bttv_risc_planar(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_planar() argument
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| /openbmc/linux/Documentation/riscv/ |
| H A D | patch-acceptance.rst | 8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
22 RISC-V has a patchwork instance, where the status of patches can be checked:
26 If your patch does not appear in the default view, the RISC-V maintainers have
31 RISC-V `for-next` and `fixes` branches, depending on whether the patch has been
32 detected as a fix. Failing those, it will use the RISC-V `master` branch.
42 specifications from the RISC-V foundation this means "Frozen" or
47 Additionally, the RISC-V specification allows implementers to create
49 to go through any review or ratification process by the RISC-V
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| H A D | boot.rst | 4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
24 The RISC-V kernel expects:
32 The RISC-V kernel expects:
39 The RISC-V kernel must not map any resident memory, or memory protected with
46 The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64
53 The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel.
71 support older firmwares without SBI HSM extension and M-mode RISC-V kernel.
75 booting the RISC-V kernel because it can support CPU hotplug and kexec.
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| H A D | hwprobe.rst | 3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
35 as defined by the RISC-V privileged architecture specification.
38 defined by the RISC-V privileged architecture specification.
41 defined by the RISC-V privileged architecture specification.
62 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
65 by version 2.2 of the RISC-V ISA manual.
68 version 1.0 of the RISC-V Vector extension manual.
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| /openbmc/linux/drivers/media/pci/cx25821/ |
| H A D | cx25821-core.c | 299 static int cx25821_risc_decode(u32 risc) in cx25821_risc_decode() argument
331 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx25821_risc_decode()
333 if (risc & (1 << (i + 12))) in cx25821_risc_decode()
336 pr_cont(" count=%d ]\n", risc & 0xfff); in cx25821_risc_decode()
337 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx25821_risc_decode()
419 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup() argument
461 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup()
487 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup_audio() argument
525 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup_audio()
555 "init risc lo", in cx25821_sram_channel_dump()
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| H A D | cx25821-video.c | 66 cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); in cx25821_start_video_dma()
76 cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ in cx25821_start_video_dma()
97 /* risc op code error */ in cx25821_video_irq()
99 pr_warn("%s, %s: video risc op code error\n", in cx25821_video_irq()
179 ret = cx25821_risc_buffer(dev->pci, &buf->risc, in cx25821_buffer_prepare()
184 ret = cx25821_risc_buffer(dev->pci, &buf->risc, in cx25821_buffer_prepare()
193 ret = cx25821_risc_buffer(dev->pci, &buf->risc, in cx25821_buffer_prepare()
199 ret = cx25821_risc_buffer(dev->pci, &buf->risc, in cx25821_buffer_prepare()
205 ret = cx25821_risc_buffer(dev->pci, &buf->risc, in cx25821_buffer_prepare()
219 (unsigned long)buf->risc.dma); in cx25821_buffer_prepare()
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| /openbmc/u-boot/doc/ |
| H A D | README.ae350 | 5 base on RISC-V architecture.
66 RISC-V # version
72 RISC-V # setenv ipaddr 10.0.4.200 ;
73 RISC-V # setenv serverip 10.0.4.97 ;
74 RISC-V # ping 10.0.4.97 ;
78 RISC-V # mmc rescan
79 RISC-V # fatls mmc 0:1
86 RISC-V # sf probe 0:0 50000000 0
89 RISC-V # sf test 0x100000 0x1000
101 RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
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| H A D | README.qemu-riscv | 5 U-Boot on QEMU's 'virt' machine on RISC-V
8 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
12 The QEMU virt machine models a generic RISC-V virtual machine with support for
15 configuration information to guest software. It implements RISC-V privileged
22 - For 32-bit RISC-V:
26 - For 64-bit RISC-V:
34 - For 32-bit RISC-V:
37 - For 64-bit RISC-V:
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| /openbmc/linux/drivers/media/pci/cx88/ |
| H A D | cx88-vbi.c | 59 VBI_LINE_LENGTH, buf->risc.dma); in cx8800_start_vbi_dma()
147 return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl, in buffer_prepare()
158 struct cx88_riscmem *risc = &buf->risc; in buffer_finish() local
160 if (risc->cpu) in buffer_finish()
161 dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu, in buffer_finish()
162 risc->dma); in buffer_finish()
163 memset(risc, 0, sizeof(*risc)); in buffer_finish()
175 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
176 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
177 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); in buffer_queue()
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| H A D | cx88-core.c | 130 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, in cx88_risc_buffer() argument
145 * estimate risc mem: worst case is one write per page border + in cx88_risc_buffer()
153 risc->size = instructions * 8; in cx88_risc_buffer()
154 risc->dma = 0; in cx88_risc_buffer()
155 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx88_risc_buffer()
157 if (!risc->cpu) in cx88_risc_buffer()
160 /* write risc instructions */ in cx88_risc_buffer()
161 rp = risc->cpu; in cx88_risc_buffer()
171 risc->jmp = rp; in cx88_risc_buffer()
172 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx88_risc_buffer()
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| /openbmc/qemu/docs/system/ |
| H A D | target-riscv.rst | 3 RISC-V System emulator
6 QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the
7 ``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine,
8 ``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine.
10 QEMU has generally good support for RISC-V guests. It has support for
12 RISC-V hardware is much more widely varying than x86 hardware. RISC-V
25 For QEMU's RISC-V system emulation, you must specify which board
29 Because RISC-V systems differ so much and in fundamental ways, typically
56 Unfortunately many of the RISC-V boards QEMU supports are currently
74 RISC-V CPU firmware
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | riscv,timer.yaml | 7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | cx23885-core.c | 38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver d…
384 static int cx23885_risc_decode(u32 risc) in cx23885_risc_decode() argument
415 printk(KERN_DEBUG "0x%08x [ %s", risc, in cx23885_risc_decode()
416 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx23885_risc_decode()
418 if (risc & (1 << (i + 12))) in cx23885_risc_decode()
420 pr_cont(" count=%d ]\n", risc & 0xfff); in cx23885_risc_decode()
421 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx23885_risc_decode()
456 unsigned int bpl, u32 risc) in cx23885_sram_channel_setup() argument
499 cx_write(ch->cmds_start + 0, risc); in cx23885_sram_channel_setup()
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| H A D | cx23885-vbi.c | 94 VBI_LINE_LENGTH, buf->risc.dma); in cx23885_start_vbi_dma()
107 cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */ in cx23885_start_vbi_dma()
144 cx23885_risc_vbibuffer(dev->pci, &buf->risc, in buffer_prepare()
162 * The risc program for each buffer works as follows: it starts with a simple
167 * This is the risc program of the first buffer to be queued if the active list
192 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
193 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in buffer_queue()
194 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); in buffer_queue()
195 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ in buffer_queue()
205 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); in buffer_queue()
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| H A D | cx23885-alsa.c | 160 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in cx23885_start_audio_dma()
165 buf->risc.dma); in cx23885_start_audio_dma()
192 cx_set(DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ in cx23885_start_audio_dma()
194 RISC enable */ in cx23885_start_audio_dma()
236 /* risc op code error */ in cx23885_audio_irq()
238 pr_warn("%s/1: Audio risc op code error\n", in cx23885_audio_irq()
261 struct cx23885_riscmem *risc; in dsp_buffer_free() local
268 risc = &chip->buf->risc; in dsp_buffer_free()
269 dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu, risc->dma); in dsp_buffer_free()
393 ret = cx23885_risc_databuffer(chip->pci, &buf->risc, buf->sglist, in snd_cx23885_hw_params()
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| /openbmc/linux/drivers/media/pci/tw68/ |
| H A D | tw68-risc.c | 24 * @rp: pointer to current risc program position
120 * @top_offset: offset within the risc program area for the
122 * @bottom_offset: offset within the risc program area for the
146 * estimate risc mem: worst case is one write per page border + in tw68_risc_buffer()
159 /* write risc instructions */ in tw68_risc_buffer()
171 /* assure risc buffer hasn't overflowed */ in tw68_risc_buffer()
180 static void tw68_risc_decode(u32 risc, u32 addr)
197 p = RISC_OP(risc);
198 if (!(risc & 0x80000000) || !instr[p].name) {
199 pr_debug("0x%08x [ INVALID ]\n", risc);
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| /openbmc/linux/Documentation/translations/it_IT/riscv/ |
| H A D | patch-acceptance.rst | 12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
35 attraverso il processo di revisione della fondazione RISC-V. Per
38 state ufficialmente accettate dalla fondazione RISC-V. (Ovviamente,
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| /openbmc/qemu/docs/specs/ |
| H A D | riscv-iommu.rst | 3 RISC-V IOMMU support for RISC-V machines
6 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
10 RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
16 This device implements the RISC-V IOMMU emulation as recommended by the section
29 This will add a RISC-V IOMMU PCI device in the board following any additional
30 PCI parameters (like PCI bus address). The behavior of the RISC-V IOMMU is
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| /openbmc/openbmc/poky/meta/conf/machine/include/riscv/ |
| H A D | tune-riscv.inc | 3 TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
4 TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
6 TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
7 TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
9 TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions"
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
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| /openbmc/linux/drivers/cpuidle/ |
| H A D | Kconfig.riscv | 3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
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| /openbmc/linux/drivers/media/pci/mantis/ |
| H A D | mantis_dma.c | 43 /* MANTIS_BUF_SIZE / MANTIS_DMA_TR_UNITS must not exceed MANTIS_RISC_SIZE (4k RISC cmd buffer) */
44 #define MANTIS_RISC_SIZE PAGE_SIZE /* RISC program must fit here. */
62 "RISC=0x%lx cpu=0x%p size=%lx", in mantis_dma_exit()
101 "RISC program allocation failed"); in mantis_alloc_buffers()
108 "RISC=0x%lx cpu=0x%p size=%lx", in mantis_alloc_buffers()
128 /* Stop RISC Engine */ in mantis_dma_init()
144 dprintk(MANTIS_DEBUG, 1, "Mantis create RISC program"); in mantis_risc_program()
147 dprintk(MANTIS_DEBUG, 1, "risc len lines %u, bytes per line %u, bytes per DMA tr %u", in mantis_risc_program()
152 dprintk(MANTIS_DEBUG, 1, "RISC PROG line=[%d], step=[%d]", line, step); in mantis_risc_program()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | dib9000.c | 93 } risc; member
239 if (state->platform.risc.fw_is_running && (reg < 1024)) in dib9000_read16_attr()
323 if (state->platform.risc.fw_is_running && (reg < 1024)) { in dib9000_write16_attr()
428 …state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-… in dib9000_risc_mem_setup_cmd()
433 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f]; in dib9000_risc_mem_setup()
435 if (state->platform.risc.memcmd == cmd && /* same command */ in dib9000_risc_mem_setup()
439 state->platform.risc.memcmd = cmd; in dib9000_risc_mem_setup()
444 if (!state->platform.risc.fw_is_running) in dib9000_risc_mem_read()
447 if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) { in dib9000_risc_mem_read()
453 mutex_unlock(&state->platform.risc.mem_lock); in dib9000_risc_mem_read()
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| /openbmc/linux/drivers/scsi/ |
| H A D | wd719x.c | 166 /* stop the RISC */ in wd719x_destroy()
169 dev_warn(&wd->pdev->dev, "RISC sleep command failed\n"); in wd719x_destroy()
170 /* disable RISC */ in wd719x_destroy()
308 const char fwname_risc[] = "wd719x-risc.bin"; in wd719x_chip_init()
319 /* RISC firmware */ in wd719x_chip_init()
337 /* make a fresh copy of WCS and RISC code */ in wd719x_chip_init()
347 /* ensure RISC is not running */ in wd719x_chip_init()
356 /* Transfer the first 2K words of RISC code to kick start the uP */ in wd719x_chip_init()
358 risc_init[1] = wd->fw_phys + ALIGN(fw_wcs->size, 4); /* RISC FW */ in wd719x_chip_init()
380 dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA aborted\n"); in wd719x_chip_init()
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