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/openbmc/linux/arch/nios2/include/asm/
H A Dasm-macros.h14 * ANDs reg2 with mask and places the result in reg1.
16 * You cannnot use the same register for reg1 & reg2.
19 .macro ANDI32 reg1, reg2, mask
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
34 * ORs reg2 with mask and places the result in reg1.
36 * It is safe to use the same register for reg1 & reg2.
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
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/openbmc/linux/arch/sparc/include/asm/
H A Dtsb.h99 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ argument
100 661: casa [TSB] ASI_N, REG1, REG2; \
103 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
106 #define TSB_CAS_TAG(TSB, REG1, REG2) \ argument
107 661: casxa [TSB] ASI_N, REG1, REG2; \
110 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
120 #define TSB_LOCK_TAG(TSB, REG1, REG2) \ argument
122 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
123 andcc REG1, REG2, %g0; \
126 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
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H A Dtrap_block.h176 * area base of the current processor into DEST. REG1, REG2, and REG3 are
184 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ argument
186 sethi %hi(trap_block), REG2; \
188 or REG2, %lo(trap_block), REG2; \
189 add REG2, REG1, REG2; \
190 ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
213 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) argument
/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_ptrauth.h26 .macro ptrauth_save_state base, reg1, reg2
28 mrs_s \reg2, SYS_APIAKEYHI_EL1
29 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)]
31 mrs_s \reg2, SYS_APIBKEYHI_EL1
32 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)]
34 mrs_s \reg2, SYS_APDAKEYHI_EL1
35 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)]
37 mrs_s \reg2, SYS_APDBKEYHI_EL1
38 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)]
40 mrs_s \reg2, SYS_APGAKEYHI_EL1
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/openbmc/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
242 TEST_ARG_REG(reg2, val2) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
250 TEST_ARG_REG(reg2, val2) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/openbmc/linux/crypto/
H A Daria_generic.c32 u32 reg0, reg1, reg2, reg3; in aria_set_encrypt_key() local
45 reg2 = w0[2] ^ ck[2]; in aria_set_encrypt_key()
48 aria_subst_diff_odd(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
69 w1[2] ^= reg2; in aria_set_encrypt_key()
74 reg2 = w1[2]; in aria_set_encrypt_key()
79 reg2 ^= ck[6]; in aria_set_encrypt_key()
82 aria_subst_diff_even(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
86 reg2 ^= w0[2]; in aria_set_encrypt_key()
91 w2[2] = reg2; in aria_set_encrypt_key()
96 reg2 ^= ck[10]; in aria_set_encrypt_key()
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/openbmc/linux/arch/arm/lib/
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldr1w \ptr, \reg2, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
66 str1w \ptr, \reg2, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dcsumpartialcopy.S29 .macro load2b, reg1, reg2 argument
31 ldrb \reg2, [r0], #1
38 .macro load2l, reg1, reg2 argument
40 ldr \reg2, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopyuser.S42 .macro load2b, reg1, reg2 argument
44 ldrusr \reg2, r0, 1
51 .macro load2l, reg1, reg2 argument
53 ldrusr \reg2, r0, 4
56 .macro load4l, reg1, reg2, reg3, reg4
58 ldrusr \reg2, r0, 4
/openbmc/linux/sound/soc/codecs/
H A Drt715-sdw.c153 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt715_sdw_read() local
169 reg2 = reg + 0x1000; in rt715_sdw_read()
170 reg2 |= 0x80; in rt715_sdw_read()
171 ret = regmap_write(rt715->sdw_regmap, reg2, val2); in rt715_sdw_read()
197 reg2 = reg + 0x1000; in rt715_sdw_read()
198 reg2 |= 0x80; in rt715_sdw_read()
199 ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff)); in rt715_sdw_read()
203 reg2 = reg - 0x1000; in rt715_sdw_read()
204 reg2 &= ~0x80; in rt715_sdw_read()
205 ret = regmap_write(rt715->sdw_regmap, reg2, in rt715_sdw_read()
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H A Drt711-sdw.c94 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt711_sdw_read() local
110 reg2 = reg + 0x1000; in rt711_sdw_read()
111 reg2 |= 0x80; in rt711_sdw_read()
112 ret = regmap_write(rt711->sdw_regmap, reg2, val2); in rt711_sdw_read()
138 reg2 = reg + 0x1000; in rt711_sdw_read()
139 reg2 |= 0x80; in rt711_sdw_read()
140 ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff)); in rt711_sdw_read()
144 reg2 = reg - 0x1000; in rt711_sdw_read()
145 reg2 &= ~0x80; in rt711_sdw_read()
147 reg2, ((*val >> 8) & 0xff)); in rt711_sdw_read()
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H A Drt700-sdw.c90 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt700_sdw_read() local
106 reg2 = reg + 0x1000; in rt700_sdw_read()
107 reg2 |= 0x80; in rt700_sdw_read()
108 ret = regmap_write(rt700->sdw_regmap, reg2, val2); in rt700_sdw_read()
134 reg2 = reg + 0x1000; in rt700_sdw_read()
135 reg2 |= 0x80; in rt700_sdw_read()
136 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff)); in rt700_sdw_read()
140 reg2 = reg - 0x1000; in rt700_sdw_read()
141 reg2 &= ~0x80; in rt700_sdw_read()
143 reg2, ((*val >> 8) & 0xff)); in rt700_sdw_read()
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/openbmc/linux/arch/s390/include/asm/
H A Dap.h136 unsigned long reg2; in ap_tapq() local
143 " lgr %[reg2],2\n" /* gr2 into reg2 */ in ap_tapq()
144 : [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2) in ap_tapq()
148 info->value = reg2; in ap_tapq()
248 struct ap_config_info *reg2 = config; in ap_qci() local
252 " lgr 2,%[reg2]\n" /* ptr to config into gr2 */ in ap_qci()
258 : [reg0] "d" (reg0), [reg2] "d" (reg2) in ap_qci()
301 unsigned long reg2 = pa_ind; in ap_aqic() local
308 " lgr 2,%[reg2]\n" /* ni addr into gr2 */ in ap_aqic()
312 : [reg0] "d" (reg0), [reg2] "d" (reg2) in ap_aqic()
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/openbmc/linux/drivers/rtc/
H A Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
34 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
36 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
43 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time()
44 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time()
45 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
65 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time()
72 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
/openbmc/u-boot/post/lib_powerpc/
H A Drlwnm.c62 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_rlwnm() local
72 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
75 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
76 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
77 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
93 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
96 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
98 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
99 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
H A Dthreex.c127 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_threex() local
137 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
141 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
142 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
158 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
161 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
162 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
163 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
H A Dthree.c157 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_three() local
167 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
171 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
172 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
188 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
192 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
193 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
/openbmc/linux/arch/x86/events/intel/
H A Duncore_nhmex.c354 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_bbox_hw_config() local
373 reg2->config = event->attr.config2; in nhmex_bbox_hw_config()
381 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_bbox_msr_enable_event() local
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
445 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_sbox_hw_config() local
458 reg2->config = event->attr.config2; in nhmex_sbox_hw_config()
466 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_sbox_msr_enable_event() local
471 wrmsrl(reg1->reg + 2, reg2->config); in nhmex_sbox_msr_enable_event()
672 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; in nhmex_mbox_get_constraint() local
693 if (reg2->idx != EXTRA_REG_NONE && in nhmex_mbox_get_constraint()
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/openbmc/phosphor-power/phosphor-regulators/test/
H A Dpmbus_error_tests.cpp26 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
29 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
38 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
46 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
48 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
55 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
H A Dwrite_verification_error_tests.cpp27 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
30 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
41 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
50 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
52 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
60 "/xyz/openbmc_project/inventory/system/chassis/motherboard/reg2"); in TEST()
/openbmc/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
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/openbmc/u-boot/arch/arm/lib/
H A Dmemcpy.S20 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
21 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
44 .macro enter reg1 reg2 argument
45 stmdb sp!, {r0, \reg1, \reg2}
48 .macro exit reg1 reg2 argument
49 ldmfd sp!, {r0, \reg1, \reg2}
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ecc.c68 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
72 reg1 = reg2 = reg3 = 0; in nand_calculate_ecc()
83 reg2 ^= ~((uint8_t) i); in nand_calculate_ecc()
89 tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ in nand_calculate_ecc()
91 tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ in nand_calculate_ecc()
93 tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ in nand_calculate_ecc()
95 tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ in nand_calculate_ecc()
98 tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ in nand_calculate_ecc()
100 tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ in nand_calculate_ecc()
102 tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ in nand_calculate_ecc()
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