| /openbmc/linux/tools/perf/Documentation/ |
| H A D | perf-list.txt | 175 ARBITRARY PMUS
179 to PMUs. Using this typically requires looking up the specific event
182 The available PMUs and their raw parameters can be listed with
195 PER SOCKET PMUS
198 Some PMUs are not associated with a core, but with a whole CPU socket.
199 Events on these PMUs generally cannot be sampled, but only counted globally
209 bandwidth would require specifying all imc PMUs (see perf list output),
229 Other PMUs and global measurements are normally root only.
242 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
300 Events from multiple different PMUs cannot be mixed in a group, with
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| H A D | perf-stat.txt | 64 of the same type of PMU in large systems (e.g. memory controller PMUs).
65 Multiple PMU instances are typical for uncore PMUs, so the prefix
479 Do not merge results from same PMUs.
492 Merge the hybrid event counts from all PMUs.
496 from all PMUs. This option enables that behavior and reports the counts
497 without PMUs.
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| H A D | intel-hybrid.txt | 10 Kernel exports two new cpu pmus via sysfs:
203 warning and disable grouping, because the pmus in group are
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| /openbmc/linux/tools/perf/pmu-events/ |
| H A D | jevents.py | 473 pmus = set()
483 pmus.add((event.pmu, pmu_name))
493 for (pmu, tbl_pmu) in sorted(pmus):
528 pmus = set()
538 pmus.add((metric.pmu, pmu_name))
548 for (pmu, tbl_pmu) in sorted(pmus):
639 const struct pmu_table_entry *pmus;
645 const struct pmu_table_entry *pmus;
676 \t\t.pmus = pmu_events__test_soc_cpu,
680 \t\t.pmus = pmu_metrics__test_soc_cpu,
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| H A D | empty-pmu-events.c | 334 * PMUs other than CORE PMUs. in perf_pmu__find_events_table()
362 * PMUs other than CORE PMUs. in perf_pmu__find_metrics_table()
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| /openbmc/linux/tools/perf/util/ |
| H A D | pmus.c | 16 #include "pmus.h"
22 * directory contains "cpus" file. All PMUs belonging to core_pmus
28 * other_pmus: All other PMUs which are not part of core_pmus list. It doesn't
31 * ibs_op// PMUs is present in each hw SMT thread, however they
32 * are captured under other_pmus. PMUs belonging to other_pmus
46 /* Non-uncore PMUs have their full length, for example, i915. */ in pmu_name_len_no_suffix()
173 /* Add all pmus in sysfs to pmu list: */
205 pr_err("Failure to set up any core PMUs\n"); in pmu_read_sysfs()
329 /* Ignore "cpu_" prefix on Intel hybrid PMUs. */ in perf_pmus__pmu_for_pmu_filter()
340 /* All core PMUs are for mem events. */ in perf_pmus__num_mem_pmus()
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| /openbmc/linux/tools/perf/arch/arm/util/ |
| H A D | auxtrace.c | 17 #include "../../../util/pmus.h"
102 static struct perf_pmu *find_pmu_for_event(struct perf_pmu **pmus, in find_pmu_for_event() argument
107 if (!pmus) in find_pmu_for_event()
111 if (evsel->core.attr.type == pmus[i]->type) in find_pmu_for_event()
112 return pmus[i]; in find_pmu_for_event()
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| /openbmc/linux/arch/x86/events/intel/ |
| H A D | uncore.c | 958 struct intel_uncore_pmu *pmu = type->pmus; in uncore_type_exit()
969 kfree(type->pmus); in uncore_type_exit()
970 type->pmus = NULL; in uncore_type_exit()
988 struct intel_uncore_pmu *pmus; in uncore_type_init() local
992 pmus = kcalloc(type->num_boxes, sizeof(*pmus), GFP_KERNEL); in uncore_type_init()
993 if (!pmus) in uncore_type_init()
999 pmus[i].func_id = setid ? i : -1; in uncore_type_init()
1000 pmus[i].pmu_idx = i; in uncore_type_init()
1001 pmus[i].type = type; in uncore_type_init()
1002 pmus[i].boxes = kzalloc(size, GFP_KERNEL); in uncore_type_init()
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | qcom_l3_pmu.rst | 5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
12 options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
25 Given that these are uncore PMUs the driver does not support sampling, therefore
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| H A D | thunderx2-pmu.rst | 6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
23 (CCPI2) events simultaneously. The PMUs provide a description of their
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| H A D | xgene-pmu.rst | 5 X-Gene SoC PMU consists of various independent system device PMUs such as
8 same model as the PMU for ARM cores. The PMUs share the same top level
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| H A D | alibaba_pmu.rst | 15 implements separate PMUs for each sub-channel to monitor various performance
50 to and from the SDRAM. The driveway PMUs have hardware logic to gather
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| H A D | hisi-pmu.rst | 5 The HiSilicon SoC chip includes various independent system device PMUs
6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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| H A D | arm_dsu_pmu.rst | 11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
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| /openbmc/linux/tools/lib/perf/include/internal/ |
| H A D | evsel.h | 47 * The cpu map read from the PMU. For core PMUs this is the list of all
48 * CPUs the event can be opened upon. For other PMUs this is the default
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| /openbmc/linux/arch/x86/kvm/ |
| H A D | pmu.h | 169 * Hybrid PMUs don't play nice with virtualization without careful in kvm_init_pmu_capability()
171 * vPMU features do not account for hybrid PMUs. Disable vPMU support in kvm_init_pmu_capability()
172 * for hybrid PMUs until KVM gains a way to let userspace opt-in. in kvm_init_pmu_capability()
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| /openbmc/linux/tools/perf/arch/x86/util/ |
| H A D | pmu.c | 17 #include "../../../util/pmus.h"
180 /* Intel uses core pmus for perf mem/c2c */ in perf_pmus__num_mem_pmus()
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| H A D | topdown.c | 5 #include "util/pmus.h"
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | imc-pmu.h | 110 * registers new IMC pmus. This structure will hold the
159 * Domains for IMC PMUs
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| /openbmc/linux/tools/perf/tests/ |
| H A D | event_groups.c | 9 #include "pmus.h"
19 /* Uncore pmus that support more than 3 counters */
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| /openbmc/linux/drivers/perf/ |
| H A D | qcom_l2_pmu.c | 107 * the hardware PMUs.
123 * This structure represents one of the hardware PMUs.
424 * physical PMUs (per cluster), because we do not support per-task mode in l2_cache_pmu_enable()
471 /* Don't allow groups with mixed PMUs, except for s/w events */ in l2_cache_event_init()
940 dev_err(&pdev->dev, "No hardware L2 cache PMUs found\n"); in l2_cache_pmu_probe()
957 dev_info(&pdev->dev, "Registered L2 cache PMU using %d HW PMUs\n", in l2_cache_pmu_probe()
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| H A D | qcom_l3_pmu.c | 3 * Driver for the L3 cache PMUs in Qualcomm Technologies chips.
448 * We must NOT create groups containing events from multiple hardware PMUs,
449 * although mixing different software and hardware PMUs is allowed.
510 * single CPU context. This is obvious for CPU PMUs, where one in qcom_l3_cache__event_init()
512 * but can lead to issues for off-core PMUs, like this one, where in qcom_l3_cache__event_init()
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| /openbmc/linux/include/linux/regulator/ |
| H A D | act8865.h | 3 * act8865.h -- Voltage regulation for active-semi act88xx PMUs
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| /openbmc/linux/tools/perf/arch/arm64/util/ |
| H A D | pmu.c | 7 #include "../../../util/pmus.h"
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | imc.rst | 42 Some PMUs may have a common scale and unit values for all their supported
53 `ibm,opal-in-memory-counters`. From the device tree, the kernel parses the PMUs
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