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/openbmc/qemu/docs/system/openrisc/
H A Demulation.rst1 OpenRISC 1000 CPU architecture support
4 QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
5 the OpenRISC 1000 cpu architecture.
9 - ORBIS32 (OpenRISC Basic Instruction Set)
10 - ORFPX32 (OpenRISC Floating-Point eXtension)
15 For information on all OpenRISC instructions please refer to the latest
16 architecture manual available on the OpenRISC website in the
17 `OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
H A Dor1k-sim.rst4 The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
12 * SMP (OpenRISC multicore using ompic)
30 The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
H A Dvirt.rst19 * SMP (OpenRISC multicore using ompic)
39 The 'virt_defconfig' for Linux openrisc kernels includes the right drivers for
H A Dcpu-features.rst4 The QEMU emulation of the OpenRISC architecture provides following built in
/openbmc/qemu/docs/system/
H A Dtarget-openrisc.rst3 OpenRISC System emulator
6 QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
8 OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
10 (the original OpenRISC instruction level simulator) which QEMU supports. For
12 OpenRISC hardware ecosystem.
14 The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
20 For QEMU's OpenRISC system emulation, you must specify which board model you
58 openrisc/or1k-sim
59 openrisc/virt
65 openrisc/emulation
[all …]
H A Dtargets.rst25 target-openrisc
/openbmc/qemu/hw/openrisc/
H A DKconfig4 depends on OPENRISC
14 depends on OPENRISC
H A Dboot.c4 * QEMU OpenRISC boot helpers.
15 #include "hw/openrisc/boot.h"
H A Dmeson.build7 hw_arch += {'openrisc': openrisc_ss}
H A Dopenrisc_sim.c2 * OpenRISC simulator for use as an IIS.
29 #include "hw/openrisc/boot.h"
237 qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic"); in openrisc_sim_ompic_init()
313 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); in openrisc_sim_init()
/openbmc/qemu/linux-user/openrisc/
H A Dtarget_mman.h2 * arch/openrisc/include/asm/processor.h:
8 /* arch/openrisc/include/asm/elf.h */
H A Dtarget_syscall.h4 /* Note that in linux/arch/openrisc/include/uapi/asm/ptrace.h,
15 #define UNAME_MACHINE "openrisc"
H A Dmeson.build2 'openrisc': generator(sh,
/openbmc/qemu/target/openrisc/
H A Dmeson.build24 target_arch += {'openrisc': openrisc_ss}
25 target_system_arch += {'openrisc': openrisc_system_ss}
H A DKconfig1 config OPENRISC config
H A Dcpu-param.h2 * OpenRISC cpu parameters for qemu.
H A Dcpu-qom.h2 * QEMU OpenRISC CPU QOM header (target agnostic)
H A Dexception.h2 * OpenRISC exception header.
/openbmc/qemu/configs/targets/
H A Dor1k-softmmu.mak1 TARGET_ARCH=openrisc
H A Dor1k-linux-user.mak1 TARGET_ARCH=openrisc
/openbmc/qemu/target/
H A DKconfig10 source openrisc/Kconfig
H A Dmeson.build11 subdir('openrisc') subdir
/openbmc/qemu/tests/functional/
H A Dtest_or1k_replay.py3 # Replay test that boots a Linux kernel on an OpenRISC-1000 SIM machine
H A Dtest_or1k_sim.py3 # Functional test that boots a Linux kernel on an OpenRISC-1000 SIM machine
/openbmc/qemu/scripts/coverity-scan/
H A DCOMPONENTS.md36 openrisc
37 ~ .*/qemu((/include)?/hw/openrisc/.*|/target/openrisc/.*)

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