| /openbmc/linux/Documentation/arch/openrisc/ |
| H A D | openrisc_port.rst | 2 OpenRISC Linux
5 This is a port of Linux to the OpenRISC class of microprocessors; the initial
6 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
8 For information about OpenRISC processors and ongoing development:
11 website https://openrisc.io
12 email openrisc@lists.librecores.org
17 Build instructions for OpenRISC toolchain and Linux
20 In order to build and run Linux for OpenRISC, you'll need at least a basic
26 Toolchain binaries can be obtained from openrisc.io or our github releases page.
27 Instructions for building the different toolchains can be found on openrisc.io
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| /openbmc/qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 1 OpenRISC 1000 CPU architecture support
4 QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
5 the OpenRISC 1000 cpu architecture.
9 - ORBIS32 (OpenRISC Basic Instruction Set)
10 - ORFPX32 (OpenRISC Floating-Point eXtension)
15 For information on all OpenRISC instructions please refer to the latest
16 architecture manual available on the OpenRISC website in the
17 `OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
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| H A D | or1k-sim.rst | 4 The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
12 * SMP (OpenRISC multicore using ompic)
30 The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
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| /openbmc/linux/Documentation/translations/zh_CN/arch/openrisc/ |
| H A D | openrisc_port.rst | 3 :Original: Documentation/arch/openrisc/openrisc_port.rst
12 OpenRISC Linux
16 OpenRISC 1000系列（或1k）。
21 网站 https://openrisc.io
22 邮箱 openrisc@lists.librecores.org
30 为了构建和运行Linux for OpenRISC，你至少需要一个基本的工具链，或许
40 二进制 https://github.com/openrisc/or1k-gcc/releases
41 工具链 https://openrisc.io/software
49 make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
50 make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
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| H A D | todo.rst | 3 :Original: Documentation/arch/openrisc/todo.rst
15 OpenRISC Linux的移植已经完全投入使用，并且从 2.6.35 开始就一直在上游同步。
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| H A D | index.rst | 5 :Original: Documentation/arch/openrisc/index.rst
14 OpenRISC 体系架构
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| /openbmc/qemu/docs/system/ |
| H A D | target-openrisc.rst | 3 OpenRISC System emulator
6 QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
8 OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
10 (the original OpenRISC instruction level simulator) which QEMU supports. For
12 OpenRISC hardware ecosystem.
14 The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
20 For QEMU's OpenRISC system emulation, you must specify which board model you
58 openrisc/or1k-sim
59 openrisc/virt
65 openrisc/emulation
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| /openbmc/linux/arch/openrisc/include/asm/ |
| H A D | io.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
22 * PCI: We do not use IO ports in OpenRISC
26 /* OpenRISC has no port IO */
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| H A D | tlb.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
19 * OpenRISC doesn't have an efficient flush_tlb_range() so use flush_tlb_mm()
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| H A D | mmu_context.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
33 extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */
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| H A D | delay.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
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| H A D | mmu.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
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| H A D | linkage.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
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| H A D | irq.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
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| H A D | irqflags.h | 3 * OpenRISC Linux
9 * OpenRISC implementation:
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| /openbmc/linux/arch/openrisc/ |
| H A D | Kconfig | 7 config OPENRISC config
79 Generic OpenRISC 1200 architecture
89 caches at relevant times. Most OpenRISC implementations support write-
202 OpenRISC architecture makes it optional to have it implemented
205 Say N here if you know that your OpenRISC processor has
212 Say Y here if your OpenRISC processor features shadowed
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| /openbmc/linux/Documentation/devicetree/bindings/openrisc/opencores/ |
| H A D | or1ksim.txt | 1 OpenRISC Generic SoC
4 Boards and FPGA SoC's which support the OpenRISC standard platform. The
5 platform essentially follows the conventions of the OpenRISC architecture
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| /openbmc/linux/arch/openrisc/mm/ |
| H A D | cache.c | 3 * OpenRISC cache.c
9 * Modifications for the OpenRISC architecture:
50 * Since icaches do not snoop for updated data on OpenRISC, we in update_cache()
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| /openbmc/linux/arch/openrisc/kernel/ |
| H A D | vmlinux.lds.S | 3 * OpenRISC vmlinux.lds.S
9 * Modifications for the OpenRISC architecture:
13 * ld script for OpenRISC architecture
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| H A D | time.c | 3 * OpenRISC time.c
9 * Modifications for the OpenRISC architecture:
135 * Clocksource: Based on OpenRISC timer/counter
137 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
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| H A D | setup.c | 3 * OpenRISC setup.c
9 * Modifications for the OpenRISC architecture:
107 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", in print_cpuinfo()
289 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); in setup_arch()
310 "OpenRISC 1000 (%d.%d-rev%d)\n", in show_cpuinfo()
319 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); in show_cpuinfo()
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| /openbmc/qemu/hw/openrisc/ |
| H A D | Kconfig | 4 depends on OPENRISC
14 depends on OPENRISC
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| /openbmc/qemu/linux-user/openrisc/ |
| H A D | target_mman.h | 2 * arch/openrisc/include/asm/processor.h:
8 /* arch/openrisc/include/asm/elf.h */
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| H A D | target_syscall.h | 4 /* Note that in linux/arch/openrisc/include/uapi/asm/ptrace.h,
15 #define UNAME_MACHINE "openrisc"
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| /openbmc/qemu/target/openrisc/ |
| H A D | meson.build | 24 target_arch += {'openrisc': openrisc_ss}
25 target_system_arch += {'openrisc': openrisc_system_ss}
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