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/openbmc/u-boot/arch/x86/include/asm/arch-braswell/fsp/
H A Dfsp_vpd.h11 u64 signature; /* Offset 0x0020 */
12 u8 revision; /* Offset 0x0028 */
13 u8 unused2[7]; /* Offset 0x0029 */
14 u16 mrc_init_tseg_size; /* Offset 0x0030 */
15 u16 mrc_init_mmio_size; /* Offset 0x0032 */
16 u8 mrc_init_spd_addr1; /* Offset 0x0034 */
17 u8 mrc_init_spd_addr2; /* Offset 0x0035 */
18 u8 mem_ch0_config; /* Offset 0x0036 */
19 u8 mem_ch1_config; /* Offset 0x0037 */
20 u32 memory_spd_ptr; /* Offset 0x0038 */
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D146.out29 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
30 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
31 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
32 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
33 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
34 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
35 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
36 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
37 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
38 …, "depth": 0, "present": true, "zero": false, "data": true, "compressed": false, "offset": OFFSET},
[all …]
H A D013.out5 At offset 0:
7 wrote 4096/4096 bytes at offset 0
9 wrote 4096/4096 bytes at offset 4096
11 wrote 4096/4096 bytes at offset 8192
13 wrote 4096/4096 bytes at offset 12288
15 wrote 4096/4096 bytes at offset 16384
17 wrote 4096/4096 bytes at offset 20480
19 wrote 4096/4096 bytes at offset 24576
21 wrote 4096/4096 bytes at offset 28672
23 wrote 4096/4096 bytes at offset 32768
[all …]
H A D022.out5 At offset 10485760:
7 wrote 4096/4096 bytes at offset 10485760
9 wrote 4096/4096 bytes at offset 10489856
11 wrote 4096/4096 bytes at offset 10493952
13 wrote 4096/4096 bytes at offset 10498048
15 wrote 4096/4096 bytes at offset 10502144
17 wrote 4096/4096 bytes at offset 10506240
19 wrote 4096/4096 bytes at offset 10510336
21 wrote 4096/4096 bytes at offset 10514432
23 wrote 4096/4096 bytes at offset 10518528
[all …]
H A D023.out7 At offset 0:
9 wrote 1024/1024 bytes at offset 0
11 wrote 1024/1024 bytes at offset 1024
13 wrote 1024/1024 bytes at offset 2048
15 wrote 1024/1024 bytes at offset 3072
17 wrote 1024/1024 bytes at offset 4096
19 wrote 1024/1024 bytes at offset 5120
21 wrote 1024/1024 bytes at offset 6144
23 wrote 1024/1024 bytes at offset 7168
25 wrote 1024/1024 bytes at offset 8192
[all …]
H A D014.out4 test2: With offset 0
7 wrote 4096/4096 bytes at offset 16384
9 wrote 4096/4096 bytes at offset 53248
11 wrote 4096/4096 bytes at offset 90112
13 wrote 4096/4096 bytes at offset 126976
15 wrote 4096/4096 bytes at offset 163840
17 wrote 4096/4096 bytes at offset 200704
19 wrote 4096/4096 bytes at offset 237568
21 wrote 4096/4096 bytes at offset 274432
23 wrote 4096/4096 bytes at offset 311296
[all …]
H A D037.out5 wrote 512/512 bytes at offset 0
7 wrote 512/512 bytes at offset 512
9 wrote 512/512 bytes at offset 1024
11 wrote 512/512 bytes at offset 1536
13 wrote 512/512 bytes at offset 2048
15 wrote 512/512 bytes at offset 2560
17 wrote 512/512 bytes at offset 3072
19 wrote 512/512 bytes at offset 3584
21 wrote 512/512 bytes at offset 4096
23 wrote 512/512 bytes at offset 4608
[all …]
/openbmc/u-boot/board/siemens/draco/
H A Dmux.c22 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
28 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
29 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
42 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
43 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
44 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
45 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h16 #define SCR 0x2C /* 0x0b offset in data sheet */
17 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
19 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
20 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
26 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
27 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/openbmc/u-boot/board/siemens/rut/
H A Dmux.c22 {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
28 {OFFSET(ddr_resetn), (MODE(0))},
29 {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
30 {OFFSET(ddr_ck), (MODE(0))},
31 {OFFSET(ddr_nck), (MODE(0))},
32 {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
33 {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
34 {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
35 {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/fsp/
H A Dfsp_vpd.h31 uint64_t signature; /* Offset 0x0000 */
32 uint8_t reserved0[24]; /* Offset 0x0008 */
33 uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
34 uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
35 uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
36 uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
37 uint8_t emmc_boot_mode; /* Offset 0x0026 */
38 uint8_t enable_sdio; /* Offset 0x0027 */
39 uint8_t enable_sdcard; /* Offset 0x0028 */
40 uint8_t enable_hsuart0; /* Offset 0x0029 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dcpu.h80 unsigned int wkclkstctrl; /* offset 0x00 */
81 unsigned int wkctrlclkctrl; /* offset 0x04 */
82 unsigned int wkgpio0clkctrl; /* offset 0x08 */
83 unsigned int wkl4wkclkctrl; /* offset 0x0c */
84 unsigned int timer0clkctrl; /* offset 0x10 */
86 unsigned int idlestdpllmpu; /* offset 0x20 */
89 unsigned int clkseldpllmpu; /* offset 0x2c */
91 unsigned int idlestdpllddr; /* offset 0x34 */
93 unsigned int clkseldpllddr; /* offset 0x40 */
95 unsigned int clkseldplldisp; /* offset 0x54 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpmc.h12 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
13 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
14 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
15 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
16 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
17 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
18 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
19 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
20 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
21 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
/openbmc/openbmc/meta-ieisystem/meta-fp5280g3/recipes-phosphor/configuration/fp5280g3-yaml-config/
H A Dfp5280g3-ipmi-inventory-sensors.yaml5 offset: 0
10 offset: 0
15 offset: 0
20 offset: 0
25 offset: 8
30 offset: 0
35 offset: 0
40 offset: 0
45 offset: 0
50 offset: 0
[all …]
/openbmc/u-boot/arch/mips/lib/
H A Dasm-offsets.c3 * offset.c: Calculate pt_regs and task_struct offsets.
20 OFFSET(PT_R0, pt_regs, regs[0]); in output_ptreg_defines()
21 OFFSET(PT_R1, pt_regs, regs[1]); in output_ptreg_defines()
22 OFFSET(PT_R2, pt_regs, regs[2]); in output_ptreg_defines()
23 OFFSET(PT_R3, pt_regs, regs[3]); in output_ptreg_defines()
24 OFFSET(PT_R4, pt_regs, regs[4]); in output_ptreg_defines()
25 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
26 OFFSET(PT_R6, pt_regs, regs[6]); in output_ptreg_defines()
27 OFFSET(PT_R7, pt_regs, regs[7]); in output_ptreg_defines()
28 OFFSET(PT_R8, pt_regs, regs[8]); in output_ptreg_defines()
[all …]
/openbmc/u-boot/board/siemens/pxm2/
H A Dmux.c23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
31 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
32 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
33 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
34 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
35 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
36 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
37 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
[all …]
/openbmc/u-boot/board/bosch/shc/
H A Dmux.c21 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
22 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
23 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
24 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
29 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
30 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
31 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
32 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
37 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
[all …]
/openbmc/u-boot/board/compulab/cm_t43/
H A Dmux.c12 {OFFSET(mii1_txen), MODE(2)},
13 {OFFSET(mii1_txd3), MODE(2)},
14 {OFFSET(mii1_txd2), MODE(2)},
15 {OFFSET(mii1_txd1), MODE(2)},
16 {OFFSET(mii1_txd0), MODE(2)},
17 {OFFSET(mii1_txclk), MODE(2)},
18 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
19 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
[all …]
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-phosphor/configuration/gbs-yaml-config/
H A Dgbs-ipmi-inventory-sensors.yaml5 offset: 0xff
10 offset: 0xff
15 offset: 0xff
20 offset: 0xff
25 offset: 0xff
30 offset: 0xff
35 offset: 0xff
40 offset: 0xff
45 offset: 0xff
50 offset: 0xff
[all …]
/openbmc/u-boot/board/BuR/brppt1/
H A Dmux.c20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
22 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
31 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
33 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
35 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
37 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
42 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
43 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-queensbay/fsp/
H A Dfsp_vpd.h13 u64 sign; /* Offset 0x0000 */
14 u64 reserved; /* Offset 0x0008 */
15 u8 dummy[240]; /* Offset 0x0010 */
16 u8 hda_verb_header[12]; /* Offset 0x0100 */
17 u32 hda_verb_length; /* Offset 0x010C */
18 u8 hda_verb_data0[16]; /* Offset 0x0110 */
19 u8 hda_verb_data1[16]; /* Offset 0x0120 */
20 u8 hda_verb_data2[16]; /* Offset 0x0130 */
21 u8 hda_verb_data3[16]; /* Offset 0x0140 */
22 u8 hda_verb_data4[16]; /* Offset 0x0150 */
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dsandbox.c25 static u8 *get_gpio_flags(struct udevice *dev, unsigned offset) in get_gpio_flags() argument
30 if (offset >= uc_priv->gpio_count) { in get_gpio_flags()
32 printf("sandbox_gpio: error: invalid gpio %u\n", offset); in get_gpio_flags()
36 return &state[offset].flags; in get_gpio_flags()
39 static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag) in get_gpio_flag() argument
41 return (*get_gpio_flags(dev, offset) & flag) != 0; in get_gpio_flag()
44 static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, in set_gpio_flag() argument
47 u8 *gpio = get_gpio_flags(dev, offset); in set_gpio_flag()
61 int sandbox_gpio_get_value(struct udevice *dev, unsigned offset) in sandbox_gpio_get_value() argument
63 if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) in sandbox_gpio_get_value()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dstv0991_cgu.h11 u32 cpu_freq; /* offset 0x0 */
12 u32 icn2_freq; /* offset 0x4 */
13 u32 dma_freq; /* offset 0x8 */
14 u32 isp_freq; /* offset 0xc */
15 u32 h264_freq; /* offset 0x10 */
16 u32 osif_freq; /* offset 0x14 */
17 u32 ren_freq; /* offset 0x18 */
18 u32 tim_freq; /* offset 0x1c */
19 u32 sai_freq; /* offset 0x20 */
20 u32 eth_freq; /* offset 0x24 */
[all …]

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