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/openbmc/qemu/include/fpu/
H A Dsoftfloat-types.h166 float_flag_invalid_cvti = 0x1000, /* non-nan to integer */
171 * because some other input was a NaN, or because the operation
187 * 2-input NaN propagation rule. Individual architectures have
188 * different rules for which input NaN is propagated to the output
189 * when there is more than one NaN on the input.
192 * NaN propagation rule, because the softfloat code guarantees
193 * not to try to pick a NaN to propagate in default NaN mode.
194 * When not in default-NaN mode, it is an error for the target
196 * we need to handle an input NaN and no rule was selected.
210 * This implements x87 NaN propagation rules:
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
62 29 SINGLE: nan / 0x7fc00000 (0 => OK)
64 30 SINGLE: nan / 0x7fa00000 (0 => OK)
67 00 SINGLE: -nan / 0xffa00000 (0 => OK)
68 00 DOUBLE: -nan / 0x00fffc000000000000 (0x1 => INVALID)
69 01 SINGLE: -nan / 0xffc00000 (0 => OK)
70 01 DOUBLE: -nan / 0x00fff8000000000000 (0 => OK)
125 29 SINGLE: nan / 0x7fc00000 (0 => OK)
126 29 DOUBLE: nan / 0x007ff8000000000000 (0 => OK)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fa00000)
183 to double: f64(nan:0x007ffc000000000000) (INVALID)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00fffc000000000000) (INVALID)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fa00000)
183 to double: f64(nan:0x007ffc000000000000) (INVALID)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00fffc000000000000) (INVALID)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
62 29 SINGLE: nan / 0x7fc00000 (0 => OK)
64 30 SINGLE: nan / 0x7fa00000 (0 => OK)
67 00 SINGLE: -nan / 0xffa00000 (0 => OK)
68 00 DOUBLE: -nan / 0x00fffc000000000000 (0x1 => INVALID)
69 01 SINGLE: -nan / 0xffc00000 (0 => OK)
70 01 DOUBLE: -nan / 0x00fff8000000000000 (0 => OK)
125 29 SINGLE: nan / 0x7fc00000 (0 => OK)
126 29 DOUBLE: nan / 0x007ff8000000000000 (0 => OK)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fa00000)
183 to double: f64(nan:0x007ffc000000000000) (INVALID)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00fffc000000000000) (INVALID)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00ffffffffffffffff) (OK)
176 from single: f32(-nan:0x7fc00000)
177 to double: f64(-nan:0x00ffffffffffffffff) (OK)
182 from single: f32(-nan:0x7fa00000)
183 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fff4000000000000) (OK)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fa00000)
183 to double: f64(nan:0x007ff4000000000000) (OK)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00fff4000000000000) (OK)
[all …]
/openbmc/qemu/tests/tcg/multiarch/libs/
H A Dfloat_helpers.c37 0xffff, /* -NaN / AHP -Max */
38 0xfcff, /* -NaN / AHP */
39 0xfc01, /* -NaN / AHP */
51 0x7c01, /* NaN / AHP */
52 0x7cff, /* NaN / AHP */
53 0x7fff, /* NaN / AHP +Max*/
81 /* Signaling NaN macros, if supported. */
89 -NAN,
116 NAN,
149 {-NAN},
[all …]
/openbmc/u-boot/post/lib_powerpc/fpu/
H A Dcompare-fp-1.c34 static float NaN; variable
124 NaN = __builtin_nan (""); in fpu_post_test_math6()
127 iuneq (NaN, NaN, 1); in fpu_post_test_math6()
138 iltgt (NaN, NaN, 0); in fpu_post_test_math6()
148 iunlt (NaN, ninf, 1); in fpu_post_test_math6()
149 iunlt (pinf, NaN, 1); in fpu_post_test_math6()
161 iunle (NaN, ninf, 1); in fpu_post_test_math6()
162 iunle (pinf, NaN, 1); in fpu_post_test_math6()
174 iungt (NaN, ninf, 1); in fpu_post_test_math6()
175 iungt (pinf, NaN, 1); in fpu_post_test_math6()
[all …]
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-catalina/plat-svc/files/
H A Diob-nic-temp-read119 …mc_project/sensors/temperature/IOB0_NIC0_OSFP_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
120 …mc_project/sensors/temperature/IOB0_NIC1_OSFP_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
121 …mc_project/sensors/temperature/IOB1_NIC0_OSFP_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
122 …mc_project/sensors/temperature/IOB1_NIC1_OSFP_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
124 …openbmc_project/sensors/temperature/IOB0_NIC0_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
125 …openbmc_project/sensors/temperature/IOB0_NIC1_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
126 …openbmc_project/sensors/temperature/IOB1_NIC0_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
127 …openbmc_project/sensors/temperature/IOB1_NIC1_TEMP_C xyz.openbmc_project.Sensor.Value Value d "nan"
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Sensor/Threshold/
H A DSoftShutdown.interface.yaml26 default: NaN
28 The upper bound of the soft shutdown threshold. A value of 'NaN' is
32 default: NaN
34 The lower bound of the soft shutdown threshold. A value of 'NaN' is
H A DPerformanceLoss.interface.yaml26 default: NaN
28 The upper bound of the warning threshold. A value of 'NaN' is used to
32 default: NaN
34 The lower bound of the warning threshold. A value of 'NaN' is used to
H A DHardShutdown.interface.yaml27 default: NaN
29 The upper bound of the shutdown threshold. A value of 'NaN' is used
33 default: NaN
35 The lower bound of the shutdown threshold. A value of 'NaN' is used
H A DWarning.interface.yaml26 default: NaN
28 The upper bound of the warning threshold. A value of 'NaN' is used to
32 default: NaN
34 The lower bound of the warning threshold. A value of 'NaN' is used to
H A DCritical.interface.yaml26 default: NaN
28 The upper bound of the critical threshold. A value of 'NaN' is used
32 default: NaN
34 The lower bound of the critical threshold. A value of 'NaN' is used
/openbmc/qemu/target/mips/
H A Dmsa.c73 * A signaling NaN is always silenced before returning it. in msa_reset()
84 /* clear float_status nan mode */ in msa_reset()
90 /* Inf * 0 + NaN returns the input NaN */ in msa_reset()
93 /* Default NaN: sign bit clear, frac msb set */ in msa_reset()
/openbmc/qemu/tests/tcg/i386/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffe00000)
3 to double: f64(-nan:0x00fffc000000000000) (OK)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fe00000)
183 to double: f64(nan:0x007ffc000000000000) (OK)
189 from single: f32(-nan:0xffe00000)
190 to double: f64(-nan:0x00fffc000000000000) (OK)
[all …]
/openbmc/qemu/tests/tcg/x86_64/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
176 from single: f32(nan:0x7fc00000)
177 to double: f64(nan:0x007ff8000000000000) (OK)
182 from single: f32(nan:0x7fa00000)
183 to double: f64(nan:0x007ffc000000000000) (INVALID)
189 from single: f32(-nan:0xffa00000)
190 to double: f64(-nan:0x00fffc000000000000) (INVALID)
[all …]
H A Dfloat_convd.ref2 from double: f64(nan:0x007ff4000000000000)
3 to single: f32(nan:0x7fe00000) (INVALID)
8 from double: f64(-nan:0x00fff8000000000000)
9 to single: f32(-nan:0xffc00000) (OK)
230 from double: f64(nan:0x007ff8000000000000)
231 to single: f32(nan:0x7fc00000) (OK)
236 from double: f64(nan:0x007ff0000000000001)
237 to single: f32(nan:0x7fc00000) (INVALID)
242 from double: f64(nan:0x007ff4000000000000)
243 to single: f32(nan:0x7fe00000) (INVALID)
[all …]

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