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/openbmc/linux/Documentation/scsi/
H A Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
/openbmc/openpower-proc-control/procedures/p9/
H A Dstart_host.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
22 #include <phosphor-logging/log.hpp>
41 const auto& master = *(targets.begin()); in startHost() local
43 log<level::INFO>("Running P9 procedure startHost", in startHost()
47 writeReg(master, P9_LL_MODE_REG, 0x00000001); in startHost()
58 writeReg(master, P9_FSI_A_SI1S, 0x20000000); in startHost()
61 writeReg(master, P9_FSI2PIB_TRUE_MASK, 0x60000000); in startHost()
64 writeReg(master, P9_FSI2PIB_INTERRUPT, 0xFFFFFFFF); in startHost()
73 log<level::INFO>("Setting SBE seeprom side to 0", in startHost()
79 log<level::INFO>("Setting SBE seeprom side to 1", in startHost()
[all …]
H A Dstart_host_mpreboot.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
28 #include <phosphor-logging/log.hpp>
47 const auto& master = *(targets.begin()); in startHostMpReboot() local
49 log<level::INFO>("Running P9 procedure startHostMpReboot", in startHostMpReboot()
53 writeReg(master, P9_LL_MODE_REG, 0x00000001); in startHostMpReboot()
64 writeReg(master, P9_FSI_A_SI1S, 0x20000000); in startHostMpReboot()
67 writeReg(master, P9_FSI2PIB_TRUE_MASK, 0x60000000); in startHostMpReboot()
70 writeReg(master, P9_FSI2PIB_INTERRUPT, 0xFFFFFFFF); in startHostMpReboot()
79 log<level::INFO>("Setting SBE seeprom side to 0", in startHostMpReboot()
85 log<level::INFO>("Setting SBE seeprom side to 1", in startHostMpReboot()
[all …]
/openbmc/linux/drivers/staging/vme_user/
H A Dvme.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
51 switch (resource->type) { in find_bridge()
53 return list_entry(resource->entry, struct vme_master_resource, in find_bridge()
54 list)->parent; in find_bridge()
56 return list_entry(resource->entry, struct vme_slave_resource, in find_bridge()
57 list)->parent; in find_bridge()
59 return list_entry(resource->entry, struct vme_dma_resource, in find_bridge()
60 list)->parent; in find_bridge()
62 return list_entry(resource->entry, struct vme_lm_resource, in find_bridge()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
11 FSI masters may require their own DT nodes (to describe the master HW itself);
12 that requirement is defined by the master's implementation, and is described by
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
[all …]
/openbmc/linux/Documentation/w1/
H A Dw1-generic.rst2 Introduction to the 1-wire (w1) subsystem
5 The 1-wire bus is a simple master-slave bus that communicates via a single
9 drain output and by sampling the logic level of the signal line.
14 All w1 slave devices must be connected to a w1 bus master device.
16 Example w1 master devices:
18 - DS9490 usb device
19 - W1-over-GPIO
20 - DS2482 (i2c to w1 bridge)
21 - Emulated devices, such as a RS232 converter, parallel port adapter, etc
25 ------------------------------
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/openbmc/openbmc/meta-yadro/recipes-core/os-release/
H A Dos-release.bbappend3 # "merge/upstream" or "master" e.g.:
6 # feature/vesnin/some-feature
8 # master
11 # the master branch and may contain tags in the form
12 # <machine>-vX.Y[-rcZ|-dev*]. All release branches without machine tags,
13 # as well as any non-release branches produce 'Unofficial' builds.
14 # So do the release branches with -rc or -dev suffix in the latest tag.
17 print ("Preparing YADRO-specific version information")
22 versionList = version_id.split('-')
24 branch_info = run_git(d, 'rev-parse --abbrev-ref HEAD').split('/')
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/openbmc/qemu/hw/intc/
H A Di8259_common.c2 * QEMU 8259 - common bits of emulated and KVM kernel model
4 * Copyright (c) 2003-2004 Fabrice Bellard
29 #include "hw/qdev-properties.h"
38 s->last_irr = 0; in pic_reset_common()
39 s->irr &= s->elcr; in pic_reset_common()
40 s->imr = 0; in pic_reset_common()
41 s->isr = 0; in pic_reset_common()
42 s->priority_add = 0; in pic_reset_common()
43 s->irq_base = 0; in pic_reset_common()
44 s->read_reg_select = 0; in pic_reset_common()
[all …]
H A Dslavio_intctl.c4 * Copyright (c) 2003-2005 Fabrice Bellard
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
43 * There is a system master controller and one for each cpu.
54 struct SLAVIO_INTCTLState *master; member
88 // per-cpu interrupt controller
98 ret = s->intreg_pending; in slavio_intctl_mem_readl()
104 trace_slavio_intctl_mem_readl(s->cpu, addr, ret); in slavio_intctl_mem_readl()
116 trace_slavio_intctl_mem_writel(s->cpu, addr, val); in slavio_intctl_mem_writel()
120 s->intreg_pending &= ~val; in slavio_intctl_mem_writel()
121 slavio_check_interrupts(s->master, 1); in slavio_intctl_mem_writel()
[all …]
H A Di8259.c4 * Copyright (c) 2003-2004 Fabrice Bellard
40 #define TYPE_I8259 "isa-i8259"
71 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { in get_priority()
77 /* return the pic wanted interrupt. return -1 if none */
82 mask = s->irr & ~s->imr; in pic_get_irq()
85 return -1; in pic_get_irq()
88 master, the IRQ coming from the slave is not taken into account in pic_get_irq()
90 mask = s->isr; in pic_get_irq()
91 if (s->special_mask) { in pic_get_irq()
92 mask &= ~s->imr; in pic_get_irq()
[all …]
H A Dtrace-events4 pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "master %d imr %"PRIu8" irr %"P…
5 pic_set_irq(bool master, int irq, int level) "master %d irq %d level %d"
7 pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr 0x%"PRIx64" val 0x%"PRIx…
8 pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"PRIx64" val 0x%x"
27 ioapic_set_irq(int vector, int level) "vector: %d level: %d"
41 slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask …
42 slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mas…
43 slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
45 …set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level …
46 slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
[all …]
/openbmc/openpower-proc-control/procedures/openfsi/
H A Dscan.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
19 #include <phosphor-logging/elog-errors.hpp>
20 #include <phosphor-logging/log.hpp>
33 constexpr auto masterScanPath = "/sys/class/fsi-master/fsi0/rescan";
34 constexpr auto hubScanPath = "/sys/class/fsi-master/fsi1/rescan";
35 constexpr auto masterCalloutPath = "/sys/class/fsi-master/fsi0/slave@00:00/raw";
41 * @param[in] path - the sysfs path to write a 1 to
63 * Performs an FSI master scan followed by an FSI hub scan.
71 // the master and hub scans. The only way we can detect something in scan()
72 // went wrong is if the master scan didn't create the hub scan file, so in scan()
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/openbmc/qemu/hw/misc/
H A Dtz-msc.c2 * ARM TrustZone master security controller emulation
21 #include "hw/misc/tz-msc.h"
22 #include "hw/qdev-properties.h"
26 bool level = s->irq_status; in tz_msc_update_irq() local
28 trace_tz_msc_update_irq(level); in tz_msc_update_irq()
29 qemu_set_irq(s->irq, level); in tz_msc_update_irq()
32 static void tz_msc_cfg_nonsec(void *opaque, int n, int level) in tz_msc_cfg_nonsec() argument
36 trace_tz_msc_cfg_nonsec(level); in tz_msc_cfg_nonsec()
37 s->cfg_nonsec = level; in tz_msc_cfg_nonsec()
40 static void tz_msc_cfg_sec_resp(void *opaque, int n, int level) in tz_msc_cfg_sec_resp() argument
[all …]
/openbmc/linux/include/linux/
H A Dw1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * struct w1_reg_num - broken out slave device id
49 * struct w1_slave - holds a single slave device on the bus
58 * @master: bus which this slave is on
74 struct w1_master *master; member
84 * struct w1_bus_master - operations available on a bus master
88 * @read_bit: Sample the line level @return the level read (0 or 1)
90 * @write_bit: Sets the line level
92 * @touch_bit: the lowest-level function for devices that really support the
93 * 1-wire protocol.
[all …]
/openbmc/docs/architecture/code-update/
H A Dcode-update-diagrams.md3 1. [High-Level Overview](#High-Level Overview)
5 ## High-Level Overview
24 │ │Software D-Bus │
33 │ D-Bus Object │
61 - [1]
62 …[Software D-Bus Object](https://github.com/openbmc/phosphor-dbus-interfaces/tree/master/yaml/xyz/o…
63 - [*] In a static layout configuration, the images are stored in RAM and the
66 …[initrdscripts](https://github.com/openbmc/openbmc/tree/master/meta-phosphor/recipes-phosphor/init…
/openbmc/linux/arch/powerpc/platforms/powermac/
H A Dpic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include <asm/pci-bridge.h>
43 unsigned int level; member
61 static int pmac_irq_cascade = -1;
88 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); in pmac_mask_and_ack_irq()
89 out_le32(&pmac_irq_hw[i]->ack, bit); in pmac_mask_and_ack_irq()
94 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) in pmac_mask_and_ack_irq()
109 out_le32(&pmac_irq_hw[i]->ack, bit); in pmac_ack_irq()
110 (void)in_le32(&pmac_irq_hw[i]->ack); in pmac_ack_irq()
123 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); in __pmac_set_irq_mask()
[all …]
/openbmc/linux/drivers/leds/
H A Dleds-tca6507.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * leds-tca6507
9 * blink or double-blink.
12 * out-only (pull-up resistor required) or as an LED with variable
13 * brightness and hardware-assisted blinking.
18 * are named MASTER, BANK0 and BANK1.
21 * with separate time for rise, on, fall, off and second-off. Thus if
22 * 3 or more different non-trivial rates are required, software must
25 * support double-blink so 'second-off' always matches 'off'.
42 * delays in the ranges: 56-72, 112-144, 168-216, 224-27504,
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dvme.rst5 -------------------
24 .. code-block:: c
30 if (vdev->id.num >= USER_BUS_MAX)
41 dev->bridge->num.
49 -------------------
53 succeeds, a non-zero value should be returned. A zero return value indicates
59 The driver can request ownership of one or more master windows
66 bus cycle types required in 'cycle'. Master windows add a further set of
73 transfers to be provided in the route attributes. This is typically VME-to-MEM
74 and/or MEM-to-VME, though some hardware can support VME-to-VME and MEM-to-MEM
[all …]
/openbmc/linux/Documentation/driver-api/soundwire/
H A Dsummary.rst10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
12 Broad level key features of SoundWire interface include:
15 commands over a single two-pin interface.
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
40 | Master |-------+-------------------------------| Slave |
42 | |-------|-------+-----------------------| |
43 +---------------+ | | +---------------+
47 +--+-------+--+
[all …]
/openbmc/linux/include/linux/reset/
H A Dbcm63xx_pmb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 /* PMB Master controller register */
30 /* Perform the low-level PMB master operation, shared between reads and
33 static inline int __bpcm_do_op(void __iomem *master, unsigned int addr, in __bpcm_do_op() argument
40 writel(cmd, master + PMB_CTRL); in __bpcm_do_op()
42 cmd = readl(master + PMB_CTRL); in __bpcm_do_op()
47 return -EIO; in __bpcm_do_op()
50 return -ETIMEDOUT; in __bpcm_do_op()
53 } while (timeout-- > 0); in __bpcm_do_op()
55 return -ETIMEDOUT; in __bpcm_do_op()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpm-master-stats.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
16 (particularly around entering hardware-driven low power modes: XO shutdown
17 and total system-wide power collapse) are first made at Master-level, and
20 The Master Stats provide a few useful bits that can be used to assess whether
21 our device has entered the desired low-power mode, how long it took to do so,
[all …]
/openbmc/linux/drivers/fsi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 FSI - the FRU Support Interface - is a simple bus for low-level
12 access to POWER-based hardware.
29 symlinks in /dev/fsi/by-path when this option is enabled.
32 tristate "GPIO-based FSI master"
36 This option enables a FSI master driver using GPIO lines.
39 tristate "FSI hub master"
41 This option enables a FSI hub master driver. Hub is a type of FSI
42 master that is connected to the upstream master via a slave. Hubs
47 tristate "FSI master based on Aspeed ColdFire coprocessor"
[all …]
/openbmc/linux/include/linux/amba/
H A Dpl022.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
30 * enum ssp_interface - interfaces allowed for this SSP Controller
47 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
55 * enum ssp_clock_params - clock parameters, to set SSP clock at a
64 * enum ssp_rx_endian - endianess of Rx FIFO Data
73 * enum ssp_tx_endian - endianess of Tx FIFO Data
81 * enum ssp_data_size - number of bits in one data element
97 * enum ssp_mode - SSP mode of operation (Communication modes)
[all …]
/openbmc/docs/architecture/
H A Dsensor-architecture.md1 # Sensor Support for OpenBMC using phosphor-hwmon
3 This document describes sensors provided by [phosphor-hwmon][15]. An alternate
4 method is to use the suite of applications provided by [dbus-sensors][16]. While
5 the configuration details between the two methods differ, the D-Bus
10 map sensors to [D-Bus][1] objects. The D-Bus object will broadcast the
15 ## D-Bus
18 Service xyz.openbmc_project.Hwmon-<hash>.Hwmon1
27 - **<type\>** : The [HWMon class][2] name in lower case.
29 - Examples include `temperature, fan_tach, voltage`.
31 - **<label\>** : User defined name of the sensor.
[all …]
/openbmc/linux/drivers/w1/
H A Dw1_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
49 * @dev: the master device
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
66 * w1_write_bit() - Generates a write-0 or write-1 cycle.
67 * @dev: the master device
70 * Only call if dev->bus_master->touch_bit is NULL
79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
[all …]

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