Searched full:mtu5 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/include/linux/mfd/ |
| H A D | rz-mtu3.h | 27 * MTU5 contains 3 timer counter registers and is totaly different
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
50 /* 8-bit MTU5 register offset macros */
51 #define RZ_MTU3_TSTR 2 /* MTU5 Timer start register */
52 #define RZ_MTU3_TCNTCMPCLR 3 /* MTU5 Timer compare match clear register */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
78 /* 16-bit MTU5 register offset macros */
79 #define RZ_MTU3_TCNTU 0 /* MTU5 Timer counter U */
80 #define RZ_MTU3_TGRU 1 /* MTU5 Timer general register U */
81 #define RZ_MTU3_TCNTV 2 /* MTU5 Timer counter V */
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | renesas,rz-mtu3.yaml | 18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
54 - [MTU5]
56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]
58 through interlocked operation with MTU0/MTU5 and MTU8.
146 - description: MTU5.TGRU input capture/compare match
147 - description: MTU5.TGRV input capture/compare match
148 - description: MTU5.TGRW input capture/compare match
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| /openbmc/linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | setup-sh7206.c | 27 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, enumerator
76 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
77 INTC_IRQ(MTU5, 198),
118 MTU5, POE2_12 } },
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