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/openbmc/qemu/docs/system/arm/
H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
H A Dxlnx-zynq.rst4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
11 - A9 MPCORE
/openbmc/qemu/hw/cpu/
H A Darm11mpcore.c120 "mpcore-priv-container", 0x2000); in mpcore_priv_initfn()
126 /* Request the legacy 11MPCore GIC behaviour: */ in mpcore_priv_initfn()
136 /* The ARM11 MPCORE TRM says the on-chip controller may have
139 * the ARM11 MPCore test chip in the Realview Versatile Express
H A Da9mpcore.c142 * memory region, not the "timer/watchdog for core X" ones 11MPcore has. in a9mp_priv_realize()
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt44 interrupts = <0 65 0x04 /* mpcore syncpt */
45 0 67 0x04>; /* mpcore general */
/openbmc/qemu/hw/arm/
H A Dfsl-imx6.c120 DeviceState *mpcore = DEVICE(&s->a9mpcore); in fsl_imx6_realize() local
148 object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); in fsl_imx6_realize()
150 object_property_set_int(OBJECT(mpcore), "num-irq", in fsl_imx6_realize()
153 if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) { in fsl_imx6_realize()
156 sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); in fsl_imx6_realize()
158 gic = mpcore; in fsl_imx6_realize()
H A Dfsl-imx6ul.c160 DeviceState *mpcore = DEVICE(&s->a7mpcore); in fsl_imx6ul_realize() local
178 object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort); in fsl_imx6ul_realize()
179 object_property_set_int(OBJECT(mpcore), "num-irq", in fsl_imx6ul_realize()
181 sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); in fsl_imx6ul_realize()
182 sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); in fsl_imx6ul_realize()
184 gic = mpcore; in fsl_imx6ul_realize()
H A Dfsl-imx7.c169 DeviceState *mpcore = DEVICE(&s->a7mpcore); in fsl_imx7_realize() local
209 object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); in fsl_imx7_realize()
210 object_property_set_int(OBJECT(mpcore), "num-irq", in fsl_imx7_realize()
212 sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); in fsl_imx7_realize()
213 sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); in fsl_imx7_realize()
215 gic = mpcore; in fsl_imx7_realize()
H A Drealview.c204 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ in realview_init()
452 .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dtimer.c9 #include "arm-mpcore.h"
H A Dpsci.c21 #include "arm-mpcore.h"
/openbmc/qemu/include/hw/timer/
H A Darm_mptimer.h2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
/openbmc/qemu/tests/functional/
H A Dtest_arm_realview.py21 self.set_machine('realview-eb-mpcore')
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dap.h23 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.h34 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
/openbmc/qemu/hw/misc/
H A Darm11scu.c74 &mpcore_scu_ops, s, "mpcore-scu", 0x100); in arm11_scu_init()
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
98 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
/openbmc/qemu/include/hw/intc/
H A Darm_gic.h25 * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
/openbmc/qemu/hw/timer/
H A Darm_mptimer.c2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
61 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt245 interrupts = <0 65 0x04 /* mpcore syncpt */
246 0 67 0x04>; /* mpcore general */
/openbmc/u-boot/arch/arm/dts/
H A Darmada-38x.dtsi388 mpcore-soc-ctrl@20d20 {
389 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/openbmc/qemu/hw/intc/
H A Darm_gic.c11 * controller, MPCore distributed interrupt controller and ARMv7-M
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
1268 * it as pending on 11MPCore. For other GIC revisions we in gic_dist_writeb()
1405 * annoying exception of the 11MPCore's GIC. in gic_dist_writeb()
1696 /* Reserved on 11MPCore */ in gic_cpu_read()
2139 * NB that the memory region size of 0x100 applies for the 11MPCore in arm_gic_realize()
/openbmc/qemu/tests/qtest/
H A Dcdrom-test.c296 "realview-eb", "realview-eb-mpcore", "realview-pb-a8", in main()

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