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/openbmc/qemu/tests/tcg/s390x/
H A Dvxeh2_vlstr.c12 static inline void vler(S390Vector *v1, const void *va, uint8_t m3) in vler() argument
14 asm volatile("vler %[v1], 0(%[va]), %[m3]\n" in vler()
17 , [m3] "i" (m3) in vler()
21 static inline void vster(S390Vector *v1, const void *va, uint8_t m3) in vster() argument
23 asm volatile("vster %[v1], 0(%[va]), %[m3]\n" in vster()
26 , [m3] "i" (m3) in vster()
30 static inline void vlbr(S390Vector *v1, void *va, const uint8_t m3) in vlbr() argument
32 asm volatile("vlbr %[v1], 0(%[va]), %[m3]\n" in vlbr()
35 , [m3] "i" (m3) in vlbr()
39 static inline void vstbr(S390Vector *v1, void *va, const uint8_t m3) in vstbr() argument
[all …]
H A Dvxeh2_vcvt.c12 const uint8_t m3, const uint8_t m4, const uint8_t m5) in vcfps() argument
14 asm volatile("vcfps %[v1], %[v2], %[m3], %[m4], %[m5]\n" in vcfps()
17 , [m3] "i" (m3) in vcfps()
23 const uint8_t m3, const uint8_t m4, const uint8_t m5) in vcfpl() argument
25 asm volatile("vcfpl %[v1], %[v2], %[m3], %[m4], %[m5]\n" in vcfpl()
28 , [m3] "i" (m3) in vcfpl()
34 const uint8_t m3, const uint8_t m4, const uint8_t m5) in vcsfp() argument
36 asm volatile("vcsfp %[v1], %[v2], %[m3], %[m4], %[m5]\n" in vcsfp()
39 , [m3] "i" (m3) in vcsfp()
45 const uint8_t m3, const uint8_t m4, const uint8_t m5) in vclfp() argument
[all …]
H A Dlcbb.c10 lcbb(long *r1, void *dxb2, int m3, int *cc) in lcbb() argument
12 asm("lcbb %[r1],%[dxb2],%[m3]\n" in lcbb()
15 : [dxb2] "R" (*(char *)dxb2), [m3] "i" (m3) in lcbb()
23 test_lcbb(void *p, int m3, int exp_r1, int exp_cc) in test_lcbb() argument
28 lcbb(&r1, p, m3, &cc); in test_lcbb()
H A Dlocfhr.c10 locfhr(long r1, long r2, int m3, int cc) in locfhr() argument
14 "locfhr %[r1],%[r2],%[m3]\n" in locfhr()
16 : [cc] "r" (cc), [r2] "r" (r2), [m3] "i" (m3) in locfhr()
H A Dvistr.c9 const uint8_t m3, const uint8_t m5) in vistr() argument
11 asm volatile("vistr %[v1], %[v2], %[m3], %[m5]\n" in vistr()
14 , [m3] "i" (m3) in vistr()
/openbmc/u-boot/board/ti/dra7xx/
H A Dmux_data.h15 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
16 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
17 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
18 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
19 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
20 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
21 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
22 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
23 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
24 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
[all …]
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero_mux_data.h56 {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
57 {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
58 {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
59 {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
60 {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
61 {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
62 {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
63 {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
64 {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
65 {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
[all …]
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dmux.c89 {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */
90 {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */
92 {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */
93 {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */
94 {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */
95 {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */
96 {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */
97 {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */
98 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */
99 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
19 "ti,am3352-wkup-m3" for AM33xx SoCs
20 "ti,am4372-wkup-m3" for AM43xx SoCs
42 compatible = "ti,am3352-wkup-m3";
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.h84 MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
85 MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
86 MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
87 MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
88 MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
89 MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
90 MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
91 MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
92 MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
93 MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
[all …]
/openbmc/u-boot/board/compulab/cm_t35/
H A Dcm_t35.c254 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in cm_t3x_set_common_muxconf()
255 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in cm_t3x_set_common_muxconf()
256 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in cm_t3x_set_common_muxconf()
257 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in cm_t3x_set_common_muxconf()
258 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in cm_t3x_set_common_muxconf()
259 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in cm_t3x_set_common_muxconf()
260 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in cm_t3x_set_common_muxconf()
261 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in cm_t3x_set_common_muxconf()
262 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in cm_t3x_set_common_muxconf()
263 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in cm_t3x_set_common_muxconf()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dwkup-m3-ipc.yaml4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
7 title: Wakeup M3 IPC device
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
15 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
22 Wkup M3 Device Node
52 - ti,am3352-wkup-m3-ipc # for AM33xx SoCs
53 - ti,am4372-wkup-m3-ipc # for AM43xx SoCs
57 The IPC register address space to communicate with the Wakeup M3 processor
98 const: ti,am4372-wkup-m3-ipc
124 compatible = "ti,am3352-wkup-m3-ipc";
[all …]
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c202 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in set_muxconf_regs()
203 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in set_muxconf_regs()
204 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in set_muxconf_regs()
205 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in set_muxconf_regs()
206 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in set_muxconf_regs()
207 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in set_muxconf_regs()
208 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in set_muxconf_regs()
209 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in set_muxconf_regs()
210 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in set_muxconf_regs()
211 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in set_muxconf_regs()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dclocks_omap3.h198 #define CORE_M2_12 0x01 /* M3 of 2 */
203 #define CORE_M2_12_ES1 0x1 /* M3 of 2 */
208 #define CORE_M2_13 0x01 /* M3 of 2 */
213 #define CORE_M2_13_ES1 0x01 /* M3 of 2 */
218 #define CORE_M2_19P2 0x01 /* M3 of 2 */
223 #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
228 #define CORE_M2_26 0x01 /* M3 of 2 */
233 #define CORE_M2_26_ES1 0x01 /* M3 of 2 */
238 #define CORE_M2_38P4 0x01 /* M3 of 2 */
243 #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
/openbmc/linux/drivers/soc/renesas/
H A DKconfig219 bool "ARM64 Platform support for R-Car M3-N"
223 This enables support for the Renesas R-Car M3-N SoC.
227 bool "ARM64 Platform support for R-Car M3-W"
231 This enables support for the Renesas R-Car M3-W SoC.
234 bool "ARM64 Platform support for R-Car M3-W+"
238 This enables support for the Renesas R-Car M3-W+ SoC.
391 bool "System Controller support for R-Car M3-N" if COMPILE_TEST
395 bool "System Controller support for R-Car M3-W" if COMPILE_TEST
399 bool "System Controller support for R-Car M3-W+" if COMPILE_TEST
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dapple,mailbox.yaml37 M3 mailboxes are an older variant with a slightly different MMIO
42 - apple,t8103-m3-mailbox
43 - apple,t8112-m3-mailbox
44 - apple,t6000-m3-mailbox
45 - const: apple,m3-mailbox-v2
/openbmc/linux/arch/sparc/kernel/
H A Dtraps_64.c1096 #define M3 145 macro
1100 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1105 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1106 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1107 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1109 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1110 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1111 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1112 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1113 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
[all …]
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h262 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
263 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
264 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
265 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
266 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
267 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
268 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
269 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
270 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
271 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
[all …]
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h31 { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */
81 { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
82 { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
85 { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
86 { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
87 { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
88 { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h305 .macro VLEx vr1, disp, index="%r0", base, m3, opc
311 MRXBOPC \m3, \opc, v1
313 .macro VLEB vr1, disp, index="%r0", base, m3
314 VLEx \vr1, \disp, \index, \base, \m3, 0x00
316 .macro VLEH vr1, disp, index="%r0", base, m3
317 VLEx \vr1, \disp, \index, \base, \m3, 0x01
319 .macro VLEF vr1, disp, index="%r0", base, m3
320 VLEx \vr1, \disp, \index, \base, \m3, 0x03
322 .macro VLEG vr1, disp, index="%r0", base, m3
323 VLEx \vr1, \disp, \index, \base, \m3, 0x02
[all …]
H A Dcpu_mf-insn.h14 * M3 field designating the counter set.
16 .macro STCCTM r1 m3 db2
17 .insn rsy,0xeb0000000017,\r1,\m3 & 0xf,\db2
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm3.inc2 # Tune Settings for Cortex-M3
6 TUNEVALID[cortexm3] = "Enable Cortex-M3 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm3', ' -mcpu=cortex-m3', '', d)}"
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.h258 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
259 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
260 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
261 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
262 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
263 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
264 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
265 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
266 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
267 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
[all …]
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dme_status.c26 [ME_HFS_STATE_M3] = "M3 without UMA",
69 [0x07] = "S0/M0->Sx/M3",
70 [0x08] = "Sx/M3->S0/M0",
72 [0x0a] = "Power cycle reset through M3",
92 [0x11] = "Bringup in M3",
95 [0x15] = "M3 clock switching error",
96 [0x18] = "M3 kernel load",
/openbmc/linux/drivers/soc/ti/
H A DKconfig44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
50 to communicate and use the Wakeup M3 for PM features like suspend

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