| /openbmc/linux/drivers/isdn/mISDN/ |
| H A D | layer2.c | 92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
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| H A D | tei.c | 109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
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| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 271.out | 9 L2 entry #0: 0x8000000000050000 0000000000000001
11 L2 entry #0: 0x8000000000050000 0000000000000003
13 L2 entry #0: 0x8000000000050000 0000000000000007
15 L2 entry #0: 0x8000000000050000 000000000000000f
17 L2 entry #0: 0x8000000000050000 000000000000007f
19 L2 entry #0: 0x8000000000050000 00000000000003ff
21 L2 entry #0: 0x8000000000050000 00000000000103ff
23 L2 entry #0: 0x8000000000050000 00000000800103ff
24 L2 entry #1: 0x8000000000060000 0000000000000003
26 L2 entry #0: 0x8000000000050000 00000002800103fd
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | cache.json | 23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
149 …move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
191 "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
239 "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
[all …]
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| /openbmc/linux/drivers/memory/ |
| H A D | bt1-l2-ctl.c | 8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/bonnell/ |
| H A D | cache.json | 52 "BriefDescription": "Cycles L2 address bus is in use.",
94 "BriefDescription": "Cycles the L2 cache data bus is busy.",
101 "BriefDescription": "Cycles the L2 transfers data to the core.",
108 "BriefDescription": "L2 cacheable instruction fetch requests",
115 "BriefDescription": "L2 cacheable instruction fetch requests",
122 "BriefDescription": "L2 cacheable instruction fetch requests",
129 "BriefDescription": "L2 cacheable instruction fetch requests",
136 "BriefDescription": "L2 cacheable instruction fetch requests",
143 "BriefDescription": "L2 cache reads",
150 "BriefDescription": "L2 cache reads",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
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| /openbmc/qemu/tests/unit/ |
| H A D | test-hbitmap.c | 20 #define L2 (BITS_PER_LONG * L1) macro
21 #define L3 (BITS_PER_LONG * L2)
245 hbitmap_test_check(data, L2 - 1); in test_hbitmap_iter_partial()
246 hbitmap_test_check(data, L2); in test_hbitmap_iter_partial()
247 hbitmap_test_check(data, L2 + 1); in test_hbitmap_iter_partial()
248 hbitmap_test_check(data, L2 + L1); in test_hbitmap_iter_partial()
249 hbitmap_test_check(data, L2 + L1 * 2 - 1); in test_hbitmap_iter_partial()
250 hbitmap_test_check(data, L2 * 2 - 1); in test_hbitmap_iter_partial()
251 hbitmap_test_check(data, L2 * 2); in test_hbitmap_iter_partial()
252 hbitmap_test_check(data, L2 * 2 + 1); in test_hbitmap_iter_partial()
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | cache.json | 45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
61 "BriefDescription": "L2 cache lines in E state filling L2",
64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
69 "BriefDescription": "L2 cache lines in I state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
77 "BriefDescription": "L2 cache lines in S state filling L2",
80 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | cache.json | 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
77 "BriefDescription": "L2 cache lines filling L2",
80 "PublicDescription": "L2 cache lines filling L2.",
85 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | cache.json | 51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
86 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | cache.json | 51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
86 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
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| /openbmc/qemu/docs/ |
| H A D | qcow2-cache.txt | 1 qcow2 L2/refcount cache configuration
15 This document attempts to give an overview of the L2 and refcount
36 The L2 tables
40 called the L1 and L2 tables.
45 There can be many L2 tables, depending on how much space has been
48 corresponding L2 table to find out where that data is located. Since
50 an L2 cache in memory to speed up disk access.
52 The size of the L2 cache can be configured, and setting the right
61 L1/L2 tables described above.
74 aforementioned L2 cache, and its size can also be configured.
[all …]
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| /openbmc/qemu/block/ |
| H A D | qed-l2-cache.c | 2 * QEMU Enhanced Disk Format L2 Cache
15 * L2 table cache usage is as follows:
17 * An open image has one L2 table cache that is used to avoid accessing the
18 * image file for recently referenced L2 tables.
22 * the L1 and L2 tables which store cluster offsets. It is here where the L2
23 * table cache serves up recently referenced L2 tables.
25 * If there is a cache miss, that L2 table is read from the image file and
26 * committed to the cache. Subsequent accesses to that L2 table will be served
29 * L2 tables are also committed to the cache when new L2 tables are allocated
30 * in the image file. Since the L2 table cache is write-through, the new L2
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | cache.json | 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
77 "BriefDescription": "L2 cache lines filling L2",
80 "PublicDescription": "L2 cache lines filling L2.",
85 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | cache.json | 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
54 "BriefDescription": "L2 cache lines filling L2",
57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
62 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
65 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
70 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
73 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
78 "BriefDescription": "L2 code requests",
81 "PublicDescription": "Counts the total number of L2 code requests.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | cache.json | 3 … number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condit…
17 "BriefDescription": "Counts the number of L2 cache misses",
24 "BriefDescription": "Counts the total number of L2 cache references.",
31 … a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictio…
70 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
79 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
111 … forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Vali…
120 …rwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid …
129 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
138 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | cache.json | 45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
61 "BriefDescription": "L2 cache lines in E state filling L2",
64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
69 "BriefDescription": "L2 cache lines in I state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
77 "BriefDescription": "L2 cache lines in S state filling L2",
80 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | cache.json | 6 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
18 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
21 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
25 "BriefDescription": "L2 cache request misses",
28 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
33 "BriefDescription": "L2 cache requests from this core",
36 …his event counts requests originating from the core that references a cache line in the L2 cache.",
74 "BriefDescription": "Loads hit L2",
78 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
83 "BriefDescription": "Loads missed L2",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | cache.json | 44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
69 "BriefDescription": "L2 cache lines filling L2",
72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
84 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
87 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
92 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce…
95 …ines that have been prefetched by the L2 hardware prefetcher but not used by demand access when ev…
100 "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
103 … requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged wit…
[all …]
|