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/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c36 #include <asm/octeon/cvmx-helper-jtag.h>
40 * Initialize the internal QLM JTAG logic to allow programming
41 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
43 * Networks. Programming incorrect values into the JTAG chain
59 * Clock divider for QLM JTAG operations. eclk is divided by in cvmx_helper_qlm_jtag_init()
74 * Write up to 32bits into the QLM jtag chain. Bits are shifted
76 * order bits followed by the high order bits. The JTAG chain is
84 * Returns The low order bits of the JTAG chain that shifted out of the
104 * Shift long sequences of zeros into the QLM JTAG chain. It is
125 * Program the QLM JTAG chain into all lanes of the QLM. You must
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dscan_manager.c38 * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
66 * scan_mgr_jtag_io() - Access the JTAG chain
67 * @flags: Control flags, used to configure the action on the JTAG
71 * Perform I/O on the JTAG chain
77 if (flags & JTAG_BP_INSN) { /* JTAG instruction */ in scan_mgr_jtag_io()
79 * The SCC JTAG register is LSB first, so make in scan_mgr_jtag_io()
105 * scan_mgr_jtag_insn_data() - Send JTAG instruction and data
210 * scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
212 * This function obtains JTAG ID from the FPGA TAP controller.
220 /* Enable HPS to talk to JTAG in the FPGA through the System Manager */ in scan_mgr_get_fpga_id()
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/openbmc/linux/drivers/soc/rockchip/
H A Dgrf.c32 * Disable auto jtag/sdmmc switching that causes issues with the
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
81 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
92 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
103 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
127 { "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) },
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt76x8.c79 FUNC("jtag", 3, 22, 8),
121 FUNC("jtag", 3, 30, 1),
128 FUNC("jtag", 3, 31, 1),
135 FUNC("jtag", 3, 32, 1),
142 FUNC("jtag", 3, 33, 1),
149 FUNC("jtag", 3, 34, 1),
163 FUNC("jtag", 3, 39, 1),
170 FUNC("jtag", 3, 40, 1),
177 FUNC("jtag", 3, 41, 1),
184 FUNC("jtag", 3, 42, 1),
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H A Dpinctrl-rt305x.c46 static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) };
72 GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
85 GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
101 GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
/openbmc/u-boot/doc/
H A DREADME.ramboot-ppc85xx15 1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
45 - In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing b…
48 1. Using JTAG
49 Boot up in core hold off mode or stop the core after reset using JTAG
51 Preconfigure DDR/L2SRAM through JTAG interface.
102 For JTAG RAMBOOT this is not required because CCSRBAR is at ff700000.
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dralink,rt2880-pinctrl.yaml38 enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
57 enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
89 const: jtag
93 enum: [jtag]
H A Dmediatek,mt7981-pinctrl.yaml91 "jtag" "jtag" 4, 5, 6, 7, 8
92 "wm_jtag_0" "jtag" 4, 5, 6, 7, 8
93 "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13
129 "wm_jtag_1" "jtag" 20, 21, 22, 23, 24
130 "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29
161 enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led,
191 const: jtag
195 enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1]
H A Dralink,rt305x-pinctrl.yaml38 enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio,
59 enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite]
100 const: jtag
104 enum: [jtag]
H A Dralink,rt5350-pinctrl.yaml38 enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led,
59 enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite]
100 const: jtag
104 enum: [jtag]
H A Dralink,rt3352-pinctrl.yaml38 enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna,
59 enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1,
101 const: jtag
105 enum: [jtag]
H A Dralink,rt3883-pinctrl.yaml38 enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag,
77 enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi,
119 const: jtag
123 enum: [jtag]
H A Dmediatek,mt7621-pinctrl.yaml38 enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
59 enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
83 const: jtag
87 enum: [jtag]
H A Dlantiq,pinctrl-xway.txt46 exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-draco.dts57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */
58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */
59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */
60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */
61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */
/openbmc/linux/arch/arm/mach-davinci/
H A Dcputype.h20 u8 variant; /* JTAG ID bits 31:28 */
21 u16 part_no; /* JTAG ID bits 27:12 */
22 u16 manufacturer; /* JTAG ID bits 11:1 */
/openbmc/linux/drivers/tty/hvc/
H A DKconfig81 bool "ARM JTAG DCC console"
86 This console uses the JTAG DCC on ARM to create a console under the HVC
87 driver. This console is used through a JTAG only on ARM. If you don't have
88 a JTAG then you probably don't want this option.
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,r9a06g032-sysctrl.yaml25 - description: Optional external JTAG input
33 - const: jtag
70 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.h618 #define B2063_PLL_JTAG_CALNRST B43_LP_RADIO(0x064) /* PLL JTAG CALNRST */
619 #define B2063_PLL_JTAG_IN_PLL1 B43_LP_RADIO(0x065) /* PLL JTAG IN PLL 1 */
620 #define B2063_PLL_JTAG_IN_PLL2 B43_LP_RADIO(0x066) /* PLL JTAG IN PLL 2 */
621 #define B2063_PLL_JTAG_PLL_CP1 B43_LP_RADIO(0x067) /* PLL JTAG PLL CP 1 */
622 #define B2063_PLL_JTAG_PLL_CP2 B43_LP_RADIO(0x068) /* PLL JTAG PLL CP 2 */
623 #define B2063_PLL_JTAG_PLL_CP3 B43_LP_RADIO(0x069) /* PLL JTAG PLL CP 3 */
624 #define B2063_PLL_JTAG_PLL_CP4 B43_LP_RADIO(0x06A) /* PLL JTAG PLL CP 4 */
625 #define B2063_PLL_JTAG_PLL_CTL1 B43_LP_RADIO(0x06B) /* PLL JTAG PLL Control 1 */
626 #define B2063_PLL_JTAG_PLL_LF1 B43_LP_RADIO(0x06C) /* PLL JTAG PLL LF 1 */
627 #define B2063_PLL_JTAG_PLL_LF2 B43_LP_RADIO(0x06D) /* PLL JTAG PLL LF 2 */
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/openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-platform-init/
H A Dampere_platform_init.sh67 gpioset $(gpiofind jtag-sel-s0)=1 # Control JTAG MUX between CPU & FPGA
69 gpioset $(gpiofind jtag-srst-n)=1 # BMC JTAG soft reset input
/openbmc/linux/arch/sparc/include/asm/
H A Dfhc.h67 #define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
68 #define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
69 #define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
70 #define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
/openbmc/u-boot/board/work-microwave/work_92105/
H A DREADME25 This file can be loaded in SRAM through a JTAG
30 DDR through a JTAG debugger (for instance by
36 SPL assumes (even when loaded through JTAG or
/openbmc/linux/drivers/tty/serial/
H A Daltera_jtaguart.c3 * altera_jtaguart.c -- Altera JTAG UART driver
30 * Altera JTAG UART register definitions according to the Altera JTAG UART
178 pr_err(DRV_NAME ": unable to attach Altera JTAG UART %d " in altera_jtaguart_startup()
213 return (port->type == PORT_ALTERA_JTAGUART) ? "Altera JTAG UART" : NULL; in altera_jtaguart_type()
483 MODULE_DESCRIPTION("Altera JTAG UART driver");
/openbmc/qemu/hw/arm/
H A Daspeed_ast10x0.c182 object_initialize_child(obj, "jtag[0]", &s->jtag[0], in aspeed_soc_ast1030_init()
184 object_initialize_child(obj, "jtag[1]", &s->jtag[1], in aspeed_soc_ast1030_init()
412 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", in aspeed_soc_ast1030_realize()
414 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", in aspeed_soc_ast1030_realize()
/openbmc/u-boot/board/imgtec/xilfpga/
H A DREADME35 This is for easy reprogrammibility via JTAG.
52 1- JTAG load the binary and jump into it.

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