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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json39 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is …
42 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is …
45 …interlock. This event counts every cycle where the issue of an operation is stalled and there is a…
48 …interlock. This event counts every cycle where the issue of an operation is stalled and there is a…
51 …e to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle wh…
54 …e to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle wh…
99 …e slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does…
102 …e slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json27 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and…
30 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and…
33 …on issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled a…
36 …on issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled a…
39 …on issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled a…
42 …on issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled a…
/openbmc/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dmicroarch.json5 "BriefDescription": "Address-generation interlock"
10 "BriefDescription": "Long-latency interlock"
15 "BriefDescription": "CSR read interlock"
50 "BriefDescription": "Integer multiplication interlock"
55 "BriefDescription": "Floating-point interlock"
/openbmc/linux/drivers/misc/genwqe/
H A Dcard_ddcb.h24 * @hsi: Hardware software interlock
25 * @shi: Software hardware interlock. Hsi and shi are used to interlock
45 __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
102 * SHI: Software to Hardware Interlock
103 * This 1 byte field is written by software to interlock the
112 * HSI: Hardware to Software interlock
113 * This 1 byte field is written by hardware to interlock the movement
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwimmc37b.c32 wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) in wimmc37b_update() argument
42 !!(interlock[NV50_DISP_INTERLOCK_WNDW] & wndw->interlock.data))); in wimmc37b_update()
85 wndw->interlock.wimm = wndw->interlock.data; in wimmc37b_init_()
H A Dwndw.c127 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, in nv50_wndw_flush_clr() argument
139 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_clr()
143 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, in nv50_wndw_flush_set() argument
146 if (interlock[NV50_DISP_INTERLOCK_CORE]) { in nv50_wndw_flush_set()
169 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_set()
170 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; in nv50_wndw_flush_set()
173 wndw->immd->update(wndw, interlock); in nv50_wndw_flush_set()
175 interlock[wndw->interlock.type] |= wndw->interlock.data; in nv50_wndw_flush_set()
714 wndw->interlock.type = interlock_type; in nv50_wndw_new_()
715 wndw->interlock.data = interlock_data; in nv50_wndw_new_()
H A Dwndw.h17 struct nv50_disp_interlock interlock; member
41 void nv50_wndw_flush_set(struct nv50_wndw *, u32 *interlock,
43 void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush,
78 int (*update)(struct nv50_wndw *, u32 *interlock);
96 int (*update)(struct nv50_wndw *, u32 *interlock);
H A Dwndwc37e.c269 wndwc37e_update(struct nv50_wndw *wndw, u32 *interlock) in wndwc37e_update() argument
277 PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | in wndwc37e_update()
278 interlock[NV50_DISP_INTERLOCK_CORE], in wndwc37e_update()
279 SET_WINDOW_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_WNDW]); in wndwc37e_update()
283 !!(interlock[NV50_DISP_INTERLOCK_WIMM] & wndw->interlock.data))); in wndwc37e_update()
H A Ddisp.c1947 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) in nv50_disp_atomic_commit_core() argument
1957 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); in nv50_disp_atomic_commit_core()
1966 core->func->update(core, interlock, true); in nv50_disp_atomic_commit_core()
1979 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) in nv50_disp_atomic_commit_wndw() argument
1987 if (interlock[wndw->interlock.type] & wndw->interlock.data) { in nv50_disp_atomic_commit_wndw()
1989 wndw->func->update(wndw, interlock); in nv50_disp_atomic_commit_wndw()
2007 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; in nv50_disp_atomic_commit_tail() local
2037 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; in nv50_disp_atomic_commit_tail()
2051 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); in nv50_disp_atomic_commit_tail()
2067 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; in nv50_disp_atomic_commit_tail()
[all …]
H A Dcore507d.c34 core507d_update(struct nv50_core *core, u32 *interlock, bool ntfy) in core507d_update() argument
49 PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] | in core507d_update()
50 interlock[NV50_DISP_INTERLOCK_OVLY] | in core507d_update()
H A Dcorec37d.c52 corec37d_update(struct nv50_core *core, u32 *interlock, bool ntfy) in corec37d_update() argument
67 PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS], in corec37d_update()
68 SET_WINDOW_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_WNDW]); in corec37d_update()
H A Dcursc37a.c28 cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) in cursc37a_update() argument
H A Dcore.h23 int (*update)(struct nv50_core *, u32 *interlock, bool ntfy);
H A Dbase507c.c36 base507c_update(struct nv50_wndw *wndw, u32 *interlock) in base507c_update() argument
44 PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]); in base507c_update()
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A Dpipeline.json30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
35 …"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/openbmc/qemu/hw/ppc/
H A Dspapr_rtas.c471 "FWNMI: ibm,nmi-interlock RTAS called with FWNMI not registered.\n"); in rtas_ibm_nmi_interlock()
480 * The vCPU that hit the NMI should invoke "ibm,nmi-interlock" in rtas_ibm_nmi_interlock()
481 * This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock" in rtas_ibm_nmi_interlock()
484 * failure causes Linux to print the error "FWNMI: nmi-interlock in rtas_ibm_nmi_interlock()
495 * vCPU issuing "ibm,nmi-interlock" is done with NMI handling, in rtas_ibm_nmi_interlock()
659 spapr_rtas_register(RTAS_IBM_NMI_INTERLOCK, "ibm,nmi-interlock", in core_rtas_register_types()
H A Dspapr_events.c847 * By taking the interlock, we assume that the MCE will be in spapr_mce_dispatch_elog()
850 * guest won't be able to release the interlock and ultimately in spapr_mce_dispatch_elog()
882 /* Wait for FWNMI interlock. */ in spapr_mce_req_event()
887 * that CPU called "ibm,nmi-interlock") in spapr_mce_req_event()
904 * If the machine was reset while waiting for the interlock, in spapr_mce_req_event()
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/
H A DChassisCapabilities.interface.yaml26 Chassis Provides Power Interlock.
/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dpipeline.json123 …cription": "This event counts aborted requests in L1D pipelines that due to store-load interlock.",
126 …scription": "This event counts aborted requests in L1D pipelines that due to store-load interlock."
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dtid_rdma.h28 * HFI1_S_TID_WAIT_INTERLCK - QP is waiting for requester interlock
29 * HFI1_R_TID_WAIT_INTERLCK - QP is waiting for responder interlock
/openbmc/openbmc/meta-raspberrypi/recipes-graphics/userland/files/
H A D0013-Implement-triple-buffering-for-wayland.patch9 interlock to operate without pushing the frame period
/openbmc/linux/drivers/char/hw_random/
H A Dn2-drv.c53 * an interlock which blocks register reads until sufficient entropy
61 * the interlock described in the previous paragraph).
64 * all three entropy sources enabled, and the interlock time set
/openbmc/linux/arch/powerpc/platforms/pseries/
H A Dras.c437 * ibm,nmi-interlock which would result in us checkstopping if a
483 printk(KERN_ERR "FWNMI: nmi-interlock failed: %d\n", ret); in fwnmi_release_errinfo()
513 * "ibm,nmi-interlock" rtas call to release. in pSeries_system_reset_exception()
/openbmc/ipmitool/
H A DREADME304 Power Interlock : inactive
354 Power Interlock : inactive
/openbmc/linux/arch/xtensa/lib/
H A Dstrncpy_user.S80 /* 1-cycle interlock */

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