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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dintel-gma.txt1 Intel GMA Bindings
4 This is the Intel Graphics Media Accelerator. This binding supports selection
9 - compatible : "intel,gma";
12 - intel,dp-hotplug : values for digital port hotplug, one cell per value for
14 - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
18 - intel,panel-power-up-delay : T1+T2 time sequence
19 - intel,panel-power-down-delay : T3 time sequence
20 - intel,panel-power-backlight-on-delay : T5 time sequence
21 - intel,panel-power-backlight-off-delay : Tx time sequence
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/openbmc/intel-ipmi-oem/
H A Dipmi-allowlist.conf163 0x2e:0xC0:0x7f7f //<Intel OEM>:<Enable/Disable Node Manager Policy Control>
164 0x2e:0xC1:0x7f7f //<Intel OEM>:<Set Node Manager Policy>
165 0x2e:0xC2:0xff7f //<Intel OEM>:<Get Node Manager Policy>
166 0x2e:0xC3:0x7f7f //<Intel OEM>:<Set Node Manager Policy Alert Threshold>
167 0x2e:0xC4:0xff7f //<Intel OEM>:<Get Node Manager Policy Alert Threshold>
168 0x2e:0xC5:0x7f7f //<Intel OEM>:<Set Node Manager PolicySuspend Periods>
169 0x2e:0xC6:0xff7f //<Intel OEM>:<Get Node Manager PolicySuspend Periods>
170 0x2e:0xC7:0x7f7f //<Intel OEM>:<Reset Node Manager Statistics>
171 0x2e:0xC8:0xff7f //<Intel OEM>:<Get Node Manager Statistics>
172 0x2e:0xC9:0xff7f //<Intel OEM>:<Get Node Manager Capabilities>
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H A DREADME.md1 # Intel IPMI OEM support library
3 This component is intended to provide Intel-specific IPMI`[3]` command handlers
5 Intel architecture.
9 `intel-ipmi-oem` serves as an extension`[1]` to OpenBMC IPMI daemon`[2]`. It is
13 Intel-specific solutions,
22 - Commands for better integration with Intel hardware
30 3. [IPMI Specification v2.0](https://www.intel.pl/content/www/pl/pl/products/docs/servers/ipmi/ipmi…
31 4. [Intel Platform Events parsing](docs/Intel_IPMI_Platform_Events.md)
/openbmc/u-boot/board/intel/
H A DKconfig14 This is the Intel Bayley Bay Customer Reference Board. It contains an
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
22 This is the Intel Cherry Hill Customer Reference Board. It is in a
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
31 This is the Intel Cougar Canyon 2 Customer Reference Board. It
32 is built on the Chief River platform with Intel Ivybridge Processor
39 This is the Intel Crown Bay Customer Reference Board. It contains
40 the Intel Atom Processor E6xx populated on the COM Express module
42 Intel Platform Controller Hub EG20T, other system components and
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/openbmc/u-boot/arch/x86/dts/
H A Dcougarcanyon2.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
18 model = "Intel Cougar Canyon 2";
19 compatible = "intel,cougarcanyon2", "intel,chiefriver";
39 compatible = "intel,core-gen3";
41 intel,apic-id = <0>;
46 compatible = "intel,core-gen3";
48 intel,apic-id = <1>;
53 compatible = "intel,core-gen3";
55 intel,apic-id = <2>;
60 compatible = "intel,core-gen3";
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H A Dedison.dts3 * Copyright (c) 2017 Intel Corporation
9 #include <dt-bindings/interrupt-router/intel-irq.h>
16 model = "Intel Edison";
17 compatible = "intel,edison";
37 intel,apic-id = <0>;
44 intel,apic-id = <2>;
59 compatible = "intel,mid-uart";
67 compatible = "intel,mid-uart";
75 compatible = "intel,mid-uart";
83 compatible = "intel,sdhci-tangier";
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H A Dbayleybay.dts10 #include <dt-bindings/interrupt-router/intel-irq.h>
20 model = "Intel Bayley Bay";
21 compatible = "intel,bayleybay", "intel,baytrail";
42 compatible = "intel,baytrail-cpu";
44 intel,apic-id = <0>;
49 compatible = "intel,baytrail-cpu";
51 intel,apic-id = <2>;
56 compatible = "intel,baytrail-cpu";
58 intel,apic-id = <4>;
63 compatible = "intel,baytrail-cpu";
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H A Dbaytrail_som-db5800-som-6867.dts11 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <0>;
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <2>;
99 compatible = "intel,baytrail-cpu";
101 intel,apic-id = <4>;
106 compatible = "intel,baytrail-cpu";
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H A Dconga-qeval20-qa3-e3845.dts11 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
73 compatible = "intel,baytrail-cpu";
75 intel,apic-id = <0>;
80 compatible = "intel,baytrail-cpu";
82 intel,apic-id = <2>;
87 compatible = "intel,baytrail-cpu";
89 intel,apic-id = <4>;
94 compatible = "intel,baytrail-cpu";
[all …]
H A Dcherryhill.dts9 #include <dt-bindings/interrupt-router/intel-irq.h>
18 model = "Intel Cherry Hill";
19 compatible = "intel,cherryhill", "intel,braswell";
42 intel,apic-id = <0>;
49 intel,apic-id = <2>;
56 intel,apic-id = <4>;
63 intel,apic-id = <6>;
78 compatible = "intel,pch9";
81 compatible = "intel,irq-router";
82 intel,pirq-config = "ibase";
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H A Ddfi-bt700.dtsi9 #include <dt-bindings/interrupt-router/intel-irq.h>
22 compatible = "intel,x86-pinctrl";
71 compatible = "intel,baytrail-cpu";
73 intel,apic-id = <0>;
78 compatible = "intel,baytrail-cpu";
80 intel,apic-id = <2>;
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <4>;
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <6>;
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H A Dminnowmax.dts10 #include <dt-bindings/interrupt-router/intel-irq.h>
19 model = "Intel Minnowboard Max";
20 compatible = "intel,minnowmax", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
99 compatible = "intel,baytrail-cpu";
101 intel,apic-id = <0>;
106 compatible = "intel,baytrail-cpu";
108 intel,apic-id = <4>;
114 compatible = "intel,pci-baytrail", "pci-x86";
124 compatible = "pci8086,0f1c", "intel,pch9";
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H A Dgalileo.dts9 #include <dt-bindings/interrupt-router/intel-irq.h>
17 model = "Intel Galileo";
18 compatible = "intel,galileo", "intel,quark";
40 intel,apic-id = <0>;
49 compatible = "intel,quark-mrc";
96 compatible = "intel,pch7";
101 compatible = "intel,irq-router";
102 intel,pirq-config = "pci";
103 intel,actl-addr = <0x58>;
104 intel,pirq-link = <0x60 8>;
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H A Dchromebook_link.dts16 compatible = "google,link", "intel,celeron-ivybridge";
34 compatible = "intel,core-gen3";
36 intel,apic-id = <0>;
41 compatible = "intel,core-gen3";
43 intel,apic-id = <1>;
48 compatible = "intel,core-gen3";
50 intel,apic-id = <2>;
55 compatible = "intel,core-gen3";
57 intel,apic-id = <3>;
67 intel,duplicate-por;
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H A Dqemu-x86_q35.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
50 intel,apic-id = <0>;
69 compatible = "intel,pch9";
73 compatible = "intel,irq-router";
75 intel,pirq-config = "pci";
76 intel,actl-8bit;
77 intel,actl-addr = <0x44>;
78 intel,pirq-link = <0x60 8>;
79 intel,pirq-mask = <0x0e40>;
80 intel,pirq-routing = <
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel,irq-router.txt1 Intel Interrupt Router Device Binding
4 The device tree node which describes the operation of the Intel Interrupt Router
10 - compatible = "intel,irq-router"
11 - intel,pirq-config : Specifies the IRQ routing register programming mechanism.
15 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
16 configuration space, required only if intel,pirq-config = "ibase".
17 - intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
20 - intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
22 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
25 - intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
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H A Dintel-lpc.txt1 Intel LPC Device Binding
4 The device tree node which describes the operation of the Intel Low Pin
8 - compatible = "intel,lpc"
9 - intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
11 - intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
15 - intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
20 - intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
46 compatible = "intel,lpc";
49 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
51 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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/openbmc/openbmc/poky/meta/files/common-licenses/
H A DIntel3 Some or all of this work - Copyright (c) 1999 - 2017, Intel Corp.
8 2.1. This is your license from Intel Corp. under its intellectual property
13 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
15 irrevocable, perpetual, worldwide license under Intel's copyrights in the
16 base code distributed originally by Intel ("Original Intel Code") to copy,
20 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
21 license (with the right to sublicense), under only those claims of Intel
22 patents that are infringed by the Original Intel Code, to make, use, sell,
26 to or modifications of the Original Intel Code. No other license or right
44 directly or indirectly, from Original Intel Code.
[all …]
H A DIntel-ACPI6 1. COPYRIGHT NOTICE Some or all of this work - Copyright © 1999-2005, Intel Corp. All rights reserv…
10 …2.1. This is your license from Intel Corp. under its intellectual property rights. You may have ad…
12 …Intel grants, free of charge, to any person ("Licensee") obtaining a copy of the source code appea…
14 …Intel grants Licensee a non-exclusive and non-transferable patent license (with the right to subli…
18 …inent statement that the modification is derived, directly or indirectly, from Original Intel Code.
24 3.4. Intel retains all right, title, and interest in and to the Original Intel Code.
26 …Intel nor any other trademark owned or controlled by Intel shall be used in advertising or otherwi…
30 …INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED HERE. ANY SOFTWARE ORIGINATING…
32 …INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS…
H A DHPND-Intel1 Copyright (c) 1993 Intel Corporation
3 Intel hereby grants you permission to copy, modify, and distribute this
4 software and its documentation. Intel grants this permission provided
7 documentation. In addition, Intel grants this permission provided that
9 made to this software or documentation, and that the name of Intel
14 Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
16 OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or
22 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
24 OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
25 PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
/openbmc/smbios-mdr/include/
H A Dcpu.hpp2 // Copyright (c) 2018 Intel Corporation
59 {0x05, "Intel 386 processor"},
60 {0x06, "Intel 486 processor"},
65 {0x0b, "Intel Pentium processor"},
69 {0x0f, "Intel Celeron processor"},
74 {0x14, "Intel Celeron M processor"},
75 {0x15, "Intel Pentium 4 HT processor"},
76 {0x16, "Intel Processor"},
93 {0x28, "Intel Core Duo processor"},
94 {0x29, "Intel Core Duo mobile processor"},
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/openbmc/u-boot/doc/device-tree-bindings/ata/
H A Dintel-sata.txt1 Intel Pantherpoint SATA Device Binding
4 The device tree node which describes the operation of the Intel Pantherpoint
8 - compatible = "intel,pantherpoint-ahci"
9 - intel,sata-mode : string, one of:
13 - intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
15 - intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
16 - intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
22 compatible = "intel,pantherpoint-ahci";
23 intel,sata-mode = "ahci";
24 intel,sata-port-map = <1>;
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/openbmc/qemu/docs/devel/migration/
H A Dqpl-compression.rst4 The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
10 from Intel 4th Gen Intel Xeon Scalable processors, codenamed Sapphire Rapids
14 <https://intel.github.io/qpl/documentation/introduction_docs/introduction.html>`_
49 $git clone --recursive https://github.com/intel/qpl.git qpl
56 <https://intel.github.io/qpl/documentation/get_started_docs/installation.html>`_
73 6a:02.0 System peripheral: Intel Corporation Device 0cfe
74 6f:02.0 System peripheral: Intel Corporation Device 0cfe
75 74:02.0 System peripheral: Intel Corporation Device 0cfe
76 79:02.0 System peripheral: Intel Corporation Device 0cfe
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/openbmc/openbmc/poky/meta/lib/oeqa/manual/
H A Dbsp-hw.json7 "email": "alexandru.c.georgescu@intel.com",
8 "name": "alexandru.c.georgescu@intel.com"
41 "email": "juan.fernandox.ramos.frayle@intel.com",
42 "name": "juan.fernandox.ramos.frayle@intel.com"
67 "email": "alexandru.c.georgescu@intel.com",
68 "name": "alexandru.c.georgescu@intel.com"
97 "email": "alexandru.c.georgescu@intel.com",
98 "name": "alexandru.c.georgescu@intel.com"
119 "email": "alexandru.c.georgescu@intel.com",
120 "name": "alexandru.c.georgescu@intel.com"
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/openbmc/qemu/docs/system/
H A Dcpu-models-x86.rst.inc26 Intel and AMD. These allow the guest VMs to have a degree of
64 Preferred CPU models for Intel x86 hosts
67 The following CPU models are preferred for use on Intel hosts.
75 Intel Xeon Processor (ClearwaterForest, 2025)
78 Intel Xeon Processor (SierraForest, 2024), SierraForest-v2 mitigates
82 Intel Xeon Processor (GraniteRapids, 2024)
85 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
90 Intel Xeon Processor (Skylake, 2016)
93 Intel Core Processor (Skylake, 2015)
96 Intel Core Processor (Broadwell, 2014)
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