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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-dk1-scmi.dts50 &iwdg2 {
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
H A Dstm32mp157c-ed1-scmi.dts55 &iwdg2 {
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
H A Dstm32mp157c-dk2-scmi.dts56 &iwdg2 {
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
H A Dstm32mp157c-ev1-scmi.dts56 &iwdg2 {
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
H A Dstm32mp157a-microgea-stm32mp1.dtsi120 &iwdg2 {
H A Dstm32mp157a-icore-stm32mp1.dtsi168 &iwdg2 {
H A Dstm32mp151a-prtt1l.dtsi98 &iwdg2 {
H A Dstm32mp157c-odyssey-som.dtsi225 &iwdg2 {
H A Dstm32mp15xx-dhcor-som.dtsi222 &iwdg2 {
H A Dstm32mp157a-stinger96.dtsi243 &iwdg2 {
H A Dstm32mp135f-dk.dts158 &iwdg2 {
H A Dstm32mp157c-ed1.dts309 &iwdg2 {
H A Dstm32mp157c-emstamp-argon.dtsi362 &iwdg2 {
H A Dstm32mp15xc-lxa-tac.dtsi348 &iwdg2 {
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi393 &iwdg2 {
H A Dstm32mp15xx-dhcom-som.dtsi418 &iwdg2 {
H A Dstm32mp15xx-dkx.dtsi459 &iwdg2 {
H A Dstm32mp131.dtsi1318 iwdg2: watchdog@5a002000 { label
1321 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
H A Dstm32mp151.dtsi1549 iwdg2: watchdog@5a002000 { label
1552 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst,stm32-iwdg.yaml53 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
/openbmc/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h73 #define IWDG2 45 macro
H A Dstm32mp1-clks.h71 #define IWDG2 58 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h71 #define IWDG2 58 macro
/openbmc/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c750 static struct clk_stm32_gate iwdg2 = { variable
752 .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
1361 STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dcpu.c125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ in dbgmcu_init()

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