| /openbmc/linux/drivers/counter/ |
| H A D | interrupt-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/irq.h>
15 #define INTERRUPT_CNT_NAME "interrupt-cnt"
20 int irq; member
22 struct counter_signal signals; member
27 static irqreturn_t interrupt_cnt_isr(int irq, void *dev_id) in interrupt_cnt_isr() argument
32 atomic_inc(&priv->count); in interrupt_cnt_isr()
44 *enable = priv->enabled; in interrupt_cnt_enable_read()
54 if (priv->enabled == enable) in interrupt_cnt_enable_write()
58 priv->enabled = true; in interrupt_cnt_enable_write()
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_breadcrumbs.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2015-2021 Intel Corporation
21 return intel_engine_irq_enable(b->irq_engine); in irq_enable()
26 intel_engine_irq_disable(b->irq_engine); in irq_disable()
35 if (GEM_WARN_ON(!intel_gt_pm_get_if_awake(b->irq_engine->gt))) in __intel_breadcrumbs_arm_irq()
39 * The breadcrumb irq will be disarmed on the interrupt after the in __intel_breadcrumbs_arm_irq()
41 * which we can add a new waiter and avoid the cost of re-enabling in __intel_breadcrumbs_arm_irq()
42 * the irq. in __intel_breadcrumbs_arm_irq()
44 WRITE_ONCE(b->irq_armed, true); in __intel_breadcrumbs_arm_irq()
47 if (!b->irq_enabled++ && b->irq_enable(b)) in __intel_breadcrumbs_arm_irq()
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| /openbmc/linux/arch/um/os-Linux/ |
| H A D | signal.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Anton Ivanov (aivanov@{brocade.com,kot-begemot.co.uk})
6 * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
16 #include <as-layout.h>
46 /* enable signals if sig isn't IRQ signal */ in sig_handler_common()
56 * These are the asynchronous signals. SIGPROF is excluded because we want to
57 * be able to profile all of UML, not just the non-critical sections. If
58 * profiling is not thread-safe, then that is not my problem. We can disable
91 * In TT_MODE_EXTERNAL, need to still call time-travel in sig_handler()
94 * Note we won't get here if signals are hard-blocked in sig_handler()
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| /openbmc/linux/drivers/tty/ |
| H A D | synclink_gt.c | 1 // SPDX-License-Identifier: GPL-1.0+
28 * DBGINFO information - most verbose output
76 #include <asm/irq.h>
145 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
251 bool irq_requested; /* true if IRQ requested */
283 unsigned char signals; /* serial signal states */ member
495 printk("%s %s data:\n",info->device_name, label); in trace_block()
510 count -= linecount; in trace_block()
521 printk("tbuf_current=%d\n", info->tbuf_current); in dump_tbufs()
522 for (i=0 ; i < info->tbuf_count ; i++) { in dump_tbufs()
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| /openbmc/qemu/include/hw/misc/ |
| H A D | tz-ppc.h | 13 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
15 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
22 * The PPC has no register interface -- it is configured purely by a
23 * collection of input signals from other hardware in the system. Typically
24 * they are either hardwired or exposed in an ad-hoc register interface by
35 * the user's decode logic asserting one of the hsel[] signals. In QEMU,
53 * accessible to non-privileged transactions
58 * + Named GPIO output "irq": set for a transaction-failed interrupt
71 #define TYPE_TZ_PPC "tz-ppc"
90 /* State: these just track the values of our input signals */
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| H A D | tz-msc.h | 14 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
16 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
24 * The MSC has no register interface -- it is configured purely by a
25 * collection of input signals from other hardware in the system. Typically
26 * they are either hardwired or exposed in an ad-hoc register interface by
39 * + Named GPIO output "irq": set for a transaction-failed interrupt
43 * addresses should be treated as secure and which as non-secure.
57 #define TYPE_TZ_MSC "tz-msc"
66 /* State: these just track the values of our input signals */
70 /* State: are we asserting irq ? */
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| /openbmc/linux/Documentation/driver-api/gpio/ |
| H A D | legacy.rst | 13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
40 input de-glitch/debounce logic, sometimes with software controls.
42 - Inputs can often be used as IRQ signals, often edge triggered but
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| H A D | intro.rst | 16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
43 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
48 - Output values are writable (high=1, low=0). Some chips also have
50 value might be driven, supporting "wire-OR" and similar schemes for the
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | signal.h | 62 #define SIGRTMAX (_NSIG-1)
68 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
69 * SA_RESTART flag to get restarting signals (which were the default long ago)
88 #define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
104 * irq handling routines.
106 * SA_INTERRUPT is also used by the irq handling routines.
114 #define SIG_BLOCK 0 /* for blocking signals */
115 #define SIG_UNBLOCK 1 /* for unblocking signals */
123 #define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-mtk-cirq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/irq.h>
71 return chip_data->base + chip_data->offsets[idx]; in mtk_cirq_reg()
83 struct mtk_cirq_chip_data *chip_data = data->chip_data; in mtk_cirq_write_mask()
84 unsigned int cirq_num = data->hwirq; in mtk_cirq_write_mask()
127 data = data->parent_data; in mtk_cirq_set_type()
128 ret = data->chip->irq_set_type(data, type); in mtk_cirq_set_type()
149 if (is_of_node(fwspec->fwnode)) { in mtk_cirq_domain_translate()
150 if (fwspec->param_count != 3) in mtk_cirq_domain_translate()
151 return -EINVAL; in mtk_cirq_domain_translate()
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
64 * input mode to generate interrupts if detecting input signals.
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
69 * The debounce EIC is used to capture the input signals' stable status
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
74 * The latch EIC is used to latch some special power down signals and
76 * to capture signals.
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| H A D | gpio-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
16 #include <linux/irq.h>
45 * struct xgpio_instance - Stores information about GPIO device
54 * @irq: IRQ used by GPIO device
55 * @irqchip: IRQ chip
56 * @enable: GPIO IRQ enable/disable bitfield
57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
70 int irq; member
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
16 connect control signals from SFP modules and to act as an LED
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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| /openbmc/linux/drivers/platform/mellanox/ |
| H A D | mlxreg-hotplug.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2020 Mellanox Technologies
11 #include <linux/hwmon-sysfs.h>
34 * struct mlxreg_hotplug_priv_data - platform private data:
35 * @irq: platform device interrupt number;
54 int irq; member
85 string_upper(label, data->label); in mlxreg_hotplug_udev_event_send()
97 dev_pdata->regmap = regmap; in mlxreg_hotplug_pdata_export()
104 struct i2c_board_info *brdinfo = data->hpdev.brdinfo; in mlxreg_hotplug_device_create()
109 mlxreg_hotplug_udev_event_send(&priv->hwmon->kobj, data, true); in mlxreg_hotplug_device_create()
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| /openbmc/linux/arch/m68k/mac/ |
| H A D | macints.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * exclusively use the autovector interrupts (the 'generic level0-level7'
8 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * 1 - VIA1
11 * - slot 0: one second interrupt (CA2)
12 * - slot 1: VBlank (CA1)
13 * - slot 2: ADB data ready (SR full)
14 * - slot 3: ADB data (CB2)
15 * - slot 4: ADB clock (CB1)
16 * - slot 5: timer 2
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
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| /openbmc/linux/drivers/parisc/ |
| H A D | iosapic_private.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
42 ** Polarity of SAPIC I/O input signals:
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
51 ** 11 = Level-triggered
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| /openbmc/linux/Documentation/power/ |
| H A D | suspend-and-interrupts.rst | 10 -----------------------------------
14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all
29 Device IRQs are re-enabled during system resume, right before the "early" phase
30 of resuming devices (that is, before starting to execute ->resume_early
35 ------------------------
38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
41 but also to IPIs and to some other special-purpose interrupts.
43 The IRQF_NO_SUSPEND flag is used to indicate that to the IRQ subsystem when
44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to
45 leave the corresponding IRQ enabled so as to allow the interrupt to work as
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
52 both the overall controller HW module and the sets-of-ports as "controllers".
54 Each GPIO controller in fact generates multiple interrupts signals for each set
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-dsp-keystone.txt | 4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
8 - 8 for C66x CorePacx CPUs 0-7
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
21 - gpio-controller: Marks the device node as a gpio controller.
22 - #gpio-cells: Should be 2.
29 compatible = "ti,keystone-dsp-gpio";
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| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
35 b) GPIO registers, which allow manipulation of the GPIO signals. In some
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
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| /openbmc/linux/include/linux/ |
| H A D | lp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * usr/include/linux/lp.h c.1991-1992 James Wiegand
16 /* Magic numbers for defining port-device mappings */
17 #define LP_PARPORT_UNSPEC -4
18 #define LP_PARPORT_AUTO -3
19 #define LP_PARPORT_OFF -2
20 #define LP_PARPORT_NONE -1
26 #define LP_IRQ(minor) lp_table[(minor)].dev->port->irq /* interrupt # */
33 #define LP_BASE(x) lp_table[(x)].dev->port->base
69 * The following constants describe the various signals of the printer port
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| /openbmc/linux/include/soc/at91/ |
| H A D | atmel_tcb.h | 17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
31 * IRQ resources.
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
50 * struct atmel_tc - information about a Timer/Counter Block
55 * @irq: irq for each of the three channels
61 * while on others, all TC channels share the same clock and IRQ.
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