Searched full:ipis (Results 1 – 11 of 11) sorted by relevance
70 /* Our XIVE source objects for IPIs and ENDs */145 /* Our XIVE source objects for IPIs and ENDs */
26 /* Internal interrupt source for IPIs and virtual devices */
12 * +------------------------------------+ IPIs53 * core IPIs and other sub-chips (NX, CAP, NPU) of the
184 the IRQ interrupt number ranges assigned to the guest for the IPIs.199 - ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)
150 b smp_waitloop @ wait for IPIs, board specific
144 accelerated Xen PV timers and inter-processor interrupts (IPIs).
109 TLB flush procedure requires sending IPIs and waiting for other CPUs to perform
520 * and the interrupt is always level-triggered. Timers and IPIs in write_IRQreg_ivpr()1092 /* Timers and IPIs support multicast. */ in openpic_iack()1358 /* timers and IPIs */ in fsl_common_init()
310 * Initialize the internal sources, for IPIs and virtual devices. in spapr_xive_realize()720 /* Interrupt number ranges for the IPIs */ in spapr_xive_dt()
559 * The internal sources (IPIs) of the interrupt controller have no
408 * (or theoretically even IPIs but guests don't use those with GSI in xen_evtchn_set_callback_level()