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/openbmc/linux/drivers/pinctrl/bcm/
H A DKconfig142 SoCs IOMUX controller. This features could be used only on SoCs which
146 bool "Broadcom Cygnus IOMUX driver"
153 Say yes here to enable the Broadcom Cygnus IOMUX driver.
155 The Broadcom Cygnus IOMUX driver supports group based IOMUX
201 The Broadcom Northstar2 IOMUX driver supports group based IOMUX
205 bool "Broadcom NSP IOMUX driver"
212 Say yes here to enable the Broadcom NSP SOC IOMUX driver.
214 The Broadcom Northstar Plus IOMUX driver supports pin based IOMUX
H A Dpinctrl-nsp-mux.c4 * This file contains the Northstar plus (NSP) IOMUX driver that supports
5 * group based PINMUX configuration. The Northstar plus IOMUX controller
39 * nsp IOMUX register description
54 * Keep track of nsp IOMUX configuration and prevent double configuration
56 * @nsp_mux: nsp IOMUX register description
66 * Group based IOMUX configuration
71 * @mux: nsp group based IOMUX configuration
94 * nsp IOMUX pinctrl core
403 * IOMUX has been configured previously and one is trying to in nsp_pinmux_set()
588 dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); in nsp_pinmux_probe()
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip.h22 * Encode variants of iomux registers into a type variable
43 * @type: iomux variant using IOMUX_* constants
46 * to a new value for autocalculating the following iomux registers.
99 * @iomux: array describing the 4 iomux sources of the bank
111 struct rockchip_iomux iomux[4]; member
123 .iomux = { \
136 .iomux = { \
149 .iomux = { \
170 .iomux = { \
196 .iomux = { \
[all …]
H A Dpinctrl-rockchip-core.c123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
135 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
136 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
206 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
211 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
215 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
[all …]
/openbmc/linux/arch/arc/boot/dts/
H A Dabilis_tb100.dtsi29 iomux: iomux@ff10601c { label
163 gpio-ranges = <&iomux 0 0 0>;
176 gpio-ranges = <&iomux 0 0 0>;
189 gpio-ranges = <&iomux 0 0 0>;
202 gpio-ranges = <&iomux 0 0 0>;
215 gpio-ranges = <&iomux 0 0 0>;
228 gpio-ranges = <&iomux 0 0 0>;
241 gpio-ranges = <&iomux 0 0 0>;
254 gpio-ranges = <&iomux 0 0 0>;
267 gpio-ranges = <&iomux 0 0 0>;
[all …]
H A Dabilis_tb101.dtsi29 iomux: iomux@ff10601c { label
172 gpio-ranges = <&iomux 0 0 0>;
185 gpio-ranges = <&iomux 0 0 0>;
198 gpio-ranges = <&iomux 0 0 0>;
211 gpio-ranges = <&iomux 0 0 0>;
224 gpio-ranges = <&iomux 0 0 0>;
237 gpio-ranges = <&iomux 0 0 0>;
250 gpio-ranges = <&iomux 0 0 0>;
263 gpio-ranges = <&iomux 0 0 0>;
276 gpio-ranges = <&iomux 0 0 0>;
[all …]
/openbmc/u-boot/board/engicam/imx6q/
H A Dimx6q.c16 #include <asm/arch/iomux.h>
19 #include <asm/mach-imx/iomux-v3.h>
52 /* config gpmi nand iomux */ in setup_gpmi_nand()
144 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
180 writel(reg, &iomux->gpr[2]); in setup_display()
182 reg = readl(&iomux->gpr[3]); in setup_display()
186 writel(reg, &iomux->gpr[3]); in setup_display()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dabilis,tb10x-iomux.txt7 - compatible: should be "abilis,tb10x-iomux";
52 iomux: iomux@ff10601c {
53 compatible = "abilis,tb10x-iomux";
78 gpio-ranges = <&iomux 0 0>;
H A Dfsl,imx27-pinctrl.txt1 * Freescale IMX27 IOMUX Controller
55 The iomux controller has gpio child nodes which are embedded in the iomux
56 control registers. They have to be defined as child nodes of the iomux device
58 properties for the iomux device node are required.
H A Dfsl,imx-pinctrl.txt1 * Freescale IOMUX Controller (IOMUXC) for i.MX
3 The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
20 Required properties for iomux controller:
46 1. We have pin function node defined under iomux controller node to represent
H A Dfsl,imx6ul-pinctrl.txt1 * Freescale i.MX6 UltraLite IOMUX Controller
7 - compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
H A Dbrcm,nsp-pinmux.txt1 Broadcom NSP (Northstar plus) IOMUX Controller
3 The NSP IOMUX controller supports group based mux configuration. In
12 GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers
H A Dbrcm,cygnus-pinmux.txt1 Broadcom Cygnus IOMUX Controller
3 The Cygnus IOMUX controller supports group based mux configuration. In
13 IOMUX registers
H A Dbrcm,ns2-pinmux.txt1 Broadcom Northstar2 IOMUX Controller
3 The Northstar2 IOMUX controller supports group based mux configuration. There
13 Northstar2 IOMUX and pin configuration registers.
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt21 Required properties for iomux controller:
28 Optional properties for iomux controller:
30 as some SoCs carry parts of the iomux controller registers there.
33 Deprecated properties for iomux controller:
34 - reg: first element is the general register space of the iomux controller
41 - reg: register of the gpio bank (different than the iomux registerset)
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,sm8250.yaml131 - const: mic-iomux
132 - const: spkr-iomux
230 reg-names = "mic-iomux", "spkr-iomux";
278 reg-names = "mic-iomux", "spkr-iomux";
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.h241 * @type: iomux variant using IOMUX_* constants
244 * to a new value for autocalculating the following iomux registers.
299 * @iomux: array describing the 4 iomux sources of the bank
327 struct rockchip_iomux iomux[4]; member
347 * struct rockchip_mux_recalced_data: represent a pin iomux data.
369 * struct rockchip_mux_recalced_data: represent a pin iomux data.
/openbmc/u-boot/board/gateworks/gw_ventana/
H A Dcommon.h88 /* configure i2c iomux */
90 /* configure uart iomux */
94 /* configure gpio iomux/defaults */
/openbmc/u-boot/board/engicam/imx6ul/
H A Dimx6ul.c17 #include <asm/arch/iomux.h>
20 #include <asm/mach-imx/iomux-v3.h>
53 /* config gpmi nand iomux */ in setup_gpmi_nand()
/openbmc/u-boot/board/embest/mx6boards/
H A Dmx6boards.c18 #include <asm/arch/iomux.h>
22 #include <asm/mach-imx/iomux-v3.h>
379 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds() local
381 setbits_le32(&iomux->gpr[2], in enable_lvds()
392 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in disable_lvds() local
400 clrbits_le32(&iomux->gpr[2], in disable_lvds()
462 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
492 writel(reg, &iomux->gpr[2]); in setup_display()
494 clrsetbits_le32(&iomux->gpr[3], in setup_display()
/openbmc/u-boot/board/aristainetos/
H A Daristainetos-v2.c14 #include <asm/arch/iomux.h>
18 #include <asm/mach-imx/iomux-v3.h>
405 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in enable_lvds() local
465 writel(reg, &iomux->gpr[2]); in enable_lvds()
467 reg = readl(&iomux->gpr[3]); in enable_lvds()
471 writel(reg, &iomux->gpr[3]); in enable_lvds()
478 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in enable_spi_display() local
557 writel(reg, &iomux->gpr[2]); in enable_spi_display()
559 reg = readl(&iomux->gpr[3]); in enable_spi_display()
563 writel(reg, &iomux->gpr[3]); in enable_spi_display()
/openbmc/u-boot/board/ge/mx53ppd/
H A Dmx53ppd_video.c14 #include <asm/arch/iomux-mx53.h>
80 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in lcd_enable() local
98 &iomux->gpr[2]); in lcd_enable()
/openbmc/u-boot/board/boundary/nitrogen6x/
H A Dnitrogen6x.c11 #include <asm/arch/iomux.h>
17 #include <asm/mach-imx/iomux-v3.h>
479 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds() local
481 u32 reg = readl(&iomux->gpr[2]); in enable_lvds()
483 writel(reg, &iomux->gpr[2]); in enable_lvds()
489 struct iomuxc *iomux = (struct iomuxc *) in enable_lvds_jeida() local
491 u32 reg = readl(&iomux->gpr[2]); in enable_lvds_jeida()
494 writel(reg, &iomux->gpr[2]); in enable_lvds_jeida()
757 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in setup_display() local
793 writel(reg, &iomux->gpr[2]); in setup_display()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Diomux.h3 * Based on Linux i.MX iomux-v3.h file:
16 * This iomux scheme is based around pads, which are the physical balls
34 * IOMUX/PAD Bit field definitions
/openbmc/u-boot/board/barco/platinum/
H A Dplatinum_picon.c11 #include <asm/arch/iomux.h>
13 #include <asm/mach-imx/iomux-v3.h>
134 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; in platinum_setup_enet() local
148 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); in platinum_setup_enet()

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