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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/oprofile/oprofile/
H A D0006-replace-sym_iterator-0-with-sym_iterator.patch3 Date: Tue, 12 Feb 2019 11:58:34 -0800
10 | { lo = hi = 0; name = ""; begin = end = (sym_iterator)0;}
16 Upstream-Status: Pending
17 Signed-off-by: Khem Raj <raj.khem@gmail.com>
18 ---
19 libpp/xml_utils.cpp | 26 +++++++++++++-------------
20 1 file changed, 13 insertions(+), 13 deletions(-)
22 diff --git a/libpp/xml_utils.cpp b/libpp/xml_utils.cpp
24 --- a/libpp/xml_utils.cpp
26 @@ -73,7 +73,7 @@ void dump_symbol(string const & prefix, sym_iterator it, bool want_nl = true)
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/openbmc/u-boot/board/freescale/mpc8572ds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
29 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
36 * num| hi| clk| cpo|wrdata|2T
55 * num| hi| clk| cpo|wrdata|2T
79 * num| hi| clk| cpo|wrdata|2T
93 * num| hi| clk| cpo|wrdata|2T
120 if (!pdimm->n_ranks) in fsl_ddr_board_options()
123 if (popts->registered_dimm_en) in fsl_ddr_board_options()
132 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
133 if (pbsp->n_ranks == pdimm->n_ranks) { in fsl_ddr_board_options()
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/openbmc/u-boot/board/freescale/t4rdb/
H A Dddr.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
45 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
62 * for all slots. We use identical speed tables for them. In future use, if
/openbmc/u-boot/board/varisys/cyrus/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
35 * num| hi| clk| wrlvl | cpo |wrdata|2T
57 * for both slots. We use identical speed tables for them. In future use, if
69 * num| hi| clk| wrlvl | cpo |wrdata|2T
106 if (!pdimm->n_ranks) in fsl_ddr_board_options()
109 if (popts->registered_dimm_en) in fsl_ddr_board_options()
119 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
120 if (pbsp->n_ranks == pdimm->n_ranks) { in fsl_ddr_board_options()
121 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
122 popts->cpo_override = pbsp->cpo; in fsl_ddr_board_options()
[all …]
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
27 * num| hi| clk| cpo|wrdata|2T
44 * for both slots. We use identical speed tables for them. In future use, if
78 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
79 if (pbsp->n_ranks == pdimm[i].n_ranks) { in fsl_ddr_board_options()
80 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
81 popts->clk_adjust = pbsp->clk_adjust; in fsl_ddr_board_options()
82 popts->cpo_override = pbsp->cpo; in fsl_ddr_board_options()
83 popts->write_data_delay = in fsl_ddr_board_options()
84 pbsp->write_data_delay; in fsl_ddr_board_options()
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/openbmc/u-boot/drivers/usb/eth/
H A DKconfig3 ---help---
12 ---help---
19 ---help---
27 ---help---
28 Say Y here if you would like to support Microchip LAN75XX Hi-Speed
30 Supports 10Base-T/ 100Base-TX/1000Base-T.
37 ---help---
40 Supports 10Base-T/ 100Base-TX/1000Base-T.
46 ---help---
53 ---help---
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/openbmc/u-boot/board/freescale/t4qds/
H A Dddr.h1 /* SPDX-License-Identifier: GPL-2.0+ */
30 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
49 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
66 * for all slots. We use identical speed tables for them. In future use, if
/openbmc/u-boot/drivers/usb/host/
H A DKconfig12 ---help---
43 bool "Support for PCI-based xHCI USB controller"
47 Enables support for the PCI-based xHCI controller.
50 bool "Support for Rockchip on-chip xHCI USB controller"
56 Enables support for the on-chip xHCI controller on Rockchip SoCs.
67 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
71 Enables support for the on-chip xHCI controller on STMicroelectronics
76 bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
80 Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
92 bool "Support for NXP Layerscape on-chip xHCI USB controller"
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H A Dr8a66597.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R8A66597 HCD (Host Controller Driver) for u-boot
93 #define XTAL 0xC000 /* b15-14: Crystal selection */
103 #define HSE 0x0080 /* b7: Hi-speed enable */
105 #define DRPD 0x0020 /* b5: D+/- pull down control */
116 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
117 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
119 #define IDMON 0x0004 /* b3: ID-pin monitor */
120 #define LNST 0x0003 /* b1-0: D+, D- line status */
122 #define FS_KSTS 0x0002 /* Full-Speed K State */
[all …]
H A Dxhci.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Based on xHCI host controller driver in linux-kernel
29 /* Max number of USB devices for any host controller - limit in section 6.1 */
31 /* Section 5.3.3 - MaxPorts */
42 * connect status, over-current status, port speed, and device removable.
43 * connect status and port speed are also sticky - meaning they're in
64 * over-current, reset, link state, and L1 change
91 /* bits 7:0 - how long is the Capabilities register */
96 /* HCSPARAMS1 - hcs_params1 - bitmasks */
102 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
18 * Fixed sdram init -- doesn't use serial presence detect.
70 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { in fixed_sdram()
125 * num| hi| clk| wrlvl | cpo |wrdata|2T
147 * for both slots. We use identical speed tables for them. In future use, if
159 * num| hi| clk| wrlvl | cpo |wrdata|2T
196 if (!pdimm->n_ranks) in fsl_ddr_board_options()
199 if (popts->registered_dimm_en) in fsl_ddr_board_options()
209 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
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/openbmc/u-boot/board/freescale/p1022ds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
16 u32 clk_adjust; /* Range: 0-8 */
17 u32 cpo; /* Range: 2-31 */
18 u32 write_data_delay; /* Range: 0-6 */
30 * num| hi| clk| cpo|wrdata|2T
52 if (!pdimm->n_ranks) in fsl_ddr_board_options()
57 popts->cs_local_opts[i].odt_rd_cfg = 0; in fsl_ddr_board_options()
58 popts->cs_local_opts[i].odt_wr_cfg = 1; in fsl_ddr_board_options()
67 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
68 if (pbsp->n_ranks == pdimm->n_ranks) { in fsl_ddr_board_options()
[all …]
/openbmc/u-boot/board/freescale/mpc8349emds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
28 * num| hi| clk| cpo|wrdata|2T
65 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
66 if (pbsp->n_ranks == pdimm[i].n_ranks) { in fsl_ddr_board_options()
67 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
68 popts->clk_adjust = pbsp->clk_adjust; in fsl_ddr_board_options()
69 popts->cpo_override = pbsp->cpo; in fsl_ddr_board_options()
70 popts->write_data_delay = in fsl_ddr_board_options()
71 pbsp->write_data_delay; in fsl_ddr_board_options()
72 popts->twot_en = pbsp->force_2t; in fsl_ddr_board_options()
[all …]
/openbmc/u-boot/cmd/
H A Dmii.c1 // SPDX-License-Identifier: GPL-2.0+
30 ushort hi; member
39 { 13, 6, 0x81, "speed selection" }, /* special */
41 { 11, 11, 0x01, "power-down" },
50 { 15, 15, 0x01, "100BASE-T4 able" },
51 { 14, 14, 0x01, "100BASE-X full duplex able" },
52 { 13, 13, 0x01, "100BASE-X half duplex able" },
55 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
56 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
85 { 9, 9, 0x01, "100BASE-T4 able" },
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/openbmc/u-boot/include/configs/
H A Dat91sam9x5ek.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
38 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
74 /* bootstrap + u-boot + env + linux in nandflash */
81 "bootz 0x22000000 - 0x21000000"
83 /* bootstrap + u-boot + env + linux in spi flash */
91 /* bootstrap + u-boot + env + linux in data flash */
99 /* bootstrap + u-boot + env + linux in mmc */
127 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/openbmc/u-boot/drivers/i2c/
H A Dlpc32xx_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
19 * Provide default speed and slave if target did not
52 /* Set I2C bus speed */
54 unsigned int speed, unsigned int chip) in __i2c_set_bus_speed() argument
58 if (speed == 0) in __i2c_set_bus_speed()
59 return -EINVAL; in __i2c_set_bus_speed()
63 half_period = (get_periph_clk_rate() / speed) / 2; in __i2c_set_bus_speed()
65 return -EINVAL; in __i2c_set_bus_speed()
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/openbmc/u-boot/board/freescale/p2041rdb/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
32 * wr_data_delay = 0-6
33 * clk adjust = 0-8
34 * cpo 2-0x1E (30)
39 * num| hi| clk| wrlvl | cpo |wrdata|2T
60 if (!pdimm->n_ranks) in fsl_ddr_board_options()
70 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
71 if (pbsp->n_ranks == pdimm->n_ranks) { in fsl_ddr_board_options()
72 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
73 popts->cpo_override = pbsp->cpo; in fsl_ddr_board_options()
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/openbmc/u-boot/drivers/timer/
H A Dtsc_timer.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <asm/u-boot-x86.h>
40 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) in native_calibrate_tsc()
54 switch (gd->arch.x86_model) { in native_calibrate_tsc()
77 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) in cpu_mhz_from_cpuid()
87 * According to Intel 64 and IA-32 System Programming Guide,
107 /* TNG - Intel Atom processor Z3400 series */
109 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
111 /* ANN - Intel Atom processor Z3500 series */
113 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
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/openbmc/u-boot/drivers/spi/
H A Dcadence_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
24 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_write_speed()
27 cadence_qspi_apb_config_baudrate_div(priv->regbase, in cadence_spi_write_speed()
30 /* Reconfigure delay timing if speed is changed. */ in cadence_spi_write_speed()
31 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
32 plat->tshsl_ns, plat->tsd2d_ns, in cadence_spi_write_speed()
33 plat->tchsh_ns, plat->tslch_ns); in cadence_spi_write_speed()
42 void *base = priv->regbase; in spi_calibration()
45 int err = 0, i, range_lo = -1, range_hi = -1; in spi_calibration()
85 if (range_lo == -1 && temp == idcode) { in spi_calibration()
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/openbmc/u-boot/include/
H A Dusb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Adapted for U-Boot driver model
45 * time for a BULK device to react - some are slow.
68 * Super Speed Device will have Super Speed Endpoint
92 * struct usb_device - information about a USB device
106 int speed; /* full/low/high */ member
135 * Child devices - if this is a hub device
149 /* slot_id - for xHCI enabled devices */
211 * board-specific hardware initialization, called by
212 * usb drivers and u-boot commands
[all …]
/openbmc/u-boot/arch/x86/cpu/baytrail/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
42 * Configure the internal clock of both SIO HS-UARTs, if they are enabled
52 /* Loop over the 2 HS-UARTs */ in arch_cpu_init_dm()
70 /* Enable speed step */ in set_max_freq()
88 perf_ctl.hi = 0; in set_max_freq()
101 * building-block level, not package. For non-BSP cores that are in cpu_x86_baytrail_probe()
153 info->cpu_freq = tsc_freq(); in baytrail_get_info()
154 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU; in baytrail_get_info()
164 * Use the algorithm described in Intel 64 and IA-32 Architectures in baytrail_get_count()
166 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping in baytrail_get_count()
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/openbmc/u-boot/board/freescale/t102xqds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
65 struct cpu_type *cpu = gd->arch.cpu; in fsl_ddr_board_options()
71 if (!pdimm->n_ranks) in fsl_ddr_board_options()
80 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
81 if (pbsp->n_ranks == pdimm->n_ranks && in fsl_ddr_board_options()
82 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { in fsl_ddr_board_options()
83 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
84 popts->clk_adjust = pbsp->clk_adjust; in fsl_ddr_board_options()
85 popts->wrlvl_start = pbsp->wrlvl_start; in fsl_ddr_board_options()
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
55 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); in fsl_ddr_get_dimm_params()
56 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); in fsl_ddr_get_dimm_params()
82 * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
109 if (!pdimm->n_ranks) in fsl_ddr_board_options()
119 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
120 if (pbsp->n_ranks == pdimm->n_ranks) { in fsl_ddr_board_options()
121 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
122 popts->cpo_override = pbsp->cpo; in fsl_ddr_board_options()
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
55 struct cpu_type *cpu = gd->arch.cpu; in fsl_ddr_board_options()
61 if (!pdimm->n_ranks) in fsl_ddr_board_options()
70 while (pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
71 if (pbsp->n_ranks == pdimm->n_ranks && in fsl_ddr_board_options()
72 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { in fsl_ddr_board_options()
73 if (ddr_freq <= pbsp->datarate_mhz_high) { in fsl_ddr_board_options()
74 popts->clk_adjust = pbsp->clk_adjust; in fsl_ddr_board_options()
75 popts->wrlvl_start = pbsp->wrlvl_start; in fsl_ddr_board_options()
[all …]
/openbmc/qemu/hw/net/
H A Dtrace-events3 # allwinner-sun8i-emac.c
14 lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
15 lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
37 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
38 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
39 open_eth_update_irq(uint32_t v) "IRQ <- 0x%x"
45 open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x"
46 open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x"
47 open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x"
48 open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x"
[all …]

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