Searched full:gicv1 (Results 1 – 5 of 5) sorted by relevance
62 #define GICC_CTLR_CBPR (1U << 4) /* GICv1: SBPR */151 /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
375 * This GIC device supports only revisions 3 and 4. The GICv1/v2 in arm_gicv3_common_realize()
73 * true if we're a GICv2, or a GICv1 with the security extensions.1699 /* GICv1 or v2; Arm implementation */ in gic_cpu_read()
191 // GICv1
1550 * There is no support for non-banked GICv1/2 register in ACPI spec. in gic_acpi_parse_madt_cpu()