| /openbmc/linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos5433-tmu.dtsi | 143 g3d_thermal: g3d-thermal {
148 g3d_alert_0: g3d-alert-0 {
153 g3d_alert_1: g3d-alert-1 {
158 g3d_alert_2: g3d-alert-2 {
163 g3d_alert_3: g3d-alert-3 {
168 g3d_alert_4: g3d-alert-4 {
173 g3d_alert_5: g3d-alert-5 {
178 g3d_alert_6: g3d-alert-6 {
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| H A D | exynos850.dtsi | 248 compatible = "samsung,exynos850-cmu-g3d";
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| H A D | exynos5433.dtsi | 519 compatible = "samsung,exynos5433-cmu-g3d";
696 label = "G3D";
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | s5pv210-cpufreq.c | 172 * ONEDRAM, MFC, G3D }
293 * 1. Temporary Change divider for MFC and G3D in s5pv210_target()
302 /* For MFC, G3D dividing */ in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
394 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX in s5pv210_target()
408 * 8. Change divider for MFC and G3D in s5pv210_target()
417 /* For MFC, G3D dividing */ in s5pv210_target()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos850-clock.yaml | 40 - samsung,exynos850-cmu-g3d
177 const: samsung,exynos850-cmu-g3d
184 - description: G3D clock (from CMU_TOP)
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| H A D | samsung,exynos5433-clock.yaml | 27 # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
48 - samsung,exynos5433-cmu-g3d
293 const: samsung,exynos5433-cmu-g3d
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| H A D | samsung,exynos5260-clock.yaml | 57 - samsung,exynos5260-clock-g3d
226 const: samsung,exynos5260-clock-g3d
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| H A D | samsung,exynos7885-clock.yaml | 83 - description: G3D clock (from CMU_TOP)
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| /openbmc/linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | samsung,exynos-bus.yaml | 54 |--- G3D
97 |--- G3D
115 |--- G3D
133 |--- G3D
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2701-g3d.c | 55 .name = "clk-mt2701-g3d",
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| H A D | Makefile | 36 obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
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| /openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| H A D | hi6220-domain-ctrl.yaml | 15 controller(e.g. codec, G3D ...) and the Power Management domain
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| /openbmc/qemu/hw/misc/ |
| H A D | exynos4210_pmu.c | 209 #define G3D_CONFIGURATION 0x3C60 /* Configure power mode of G3D */
210 #define G3D_STATUS 0x3C64 /* Check power mode of G3D */
211 #define G3D_OPTION 0x3C68 /* Sets control options for G3D */
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| /openbmc/linux/Documentation/devicetree/bindings/devfreq/event/ |
| H A D | samsung,exynos-ppmu.yaml | 18 each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
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| /openbmc/linux/drivers/clk/hisilicon/ |
| H A D | clk-hi3660-stub.c | 107 DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
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| /openbmc/u-boot/board/samsung/trats/ |
| H A D | trats.c | 98 writel(0x0, &pwr->g3d_configuration); /* G3D */ in trats_low_power_mode()
106 writel(0x0, &clk->gate_ip_g3d); /* G3D */ in trats_low_power_mode()
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| H A D | setup.h | 578 * GATE G3D : All block
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos5420.c | 1268 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
1273 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1354 .pd_name = "G3D",
1667 * Keep top part of G3D clock path enabled permanently to ensure in exynos5x_clk_init()
1669 * main G3D clock enablement status. in exynos5x_clk_init()
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| H A D | clk-exynos850.c | 307 /* G3D */
385 /* G3D */
449 /* G3D */
1853 .compatible = "samsung,exynos850-cmu-g3d",
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| H A D | clk-s5pv210.c | 630 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
692 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
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| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5260.dtsi | 207 compatible = "samsung,exynos5260-clock-g3d";
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| H A D | exynos3250.dtsi | 379 label = "G3D";
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | exynos4_setup.h | 306 /* SCLK G3D */
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| /openbmc/linux/drivers/thermal/ |
| H A D | hisi_thermal.c | 250 * 0x3: remote sensor 3 (G3D)
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| /openbmc/linux/drivers/devfreq/event/ |
| H A D | exynos-ppmu.c | 56 PPMU_EVENT(g3d),
|