| /openbmc/qemu/tests/tcg/xtensa/ |
| H A D | test_fp0_conv.S | 80 test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
81 test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
84 test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
87 test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
88 test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
89 test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
92 test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
93 test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
94 test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
95 test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
[all …]
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| H A D | test_fp0_arith.S | 31 test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
51 test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
68 test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
94 test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
112 test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
115 test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
126 test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
144 test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
150 test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \
158 test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
[all …]
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| H A D | test_dfp0_arith.S | 45 test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \
61 test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \
82 test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \
100 test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \
106 test_op3 madd.d, f0, f1, f2, f0, \
114 test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \
117 test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \
120 test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \
124 test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \
127 test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \
[all …]
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| H A D | test_fp1.S | 42 test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */
50 test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */
101 test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
103 test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0
108 test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0
110 test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
115 test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
117 test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
119 test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
124 test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0
[all …]
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| H A D | test_lsc.S | 16 lsip f0, a2, 8
18 lsi f0, a2, 0
23 rfr a2, f0
164 ldip f0, a2, 16
167 rfrd a2, f0
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| H A D | test_fp0_div.S | 59 test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \
70 test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \
75 test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \
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| /openbmc/webui-vue/src/views/Settings/Network/ |
| H A D | ModalDefaultGateway.vue | 60 …F0-9]{1,4}:){7}[a-fA-F0-9]{1,4}|(?:[a-fA-F0-9]{1,4}:){1,7}:|(?:[a-fA-F0-9]{1,4}:){1,6}:[a-fA-F0-9]…
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| H A D | ModalIpv6.vue | 78 …F0-9]{1,4}:){7}[a-fA-F0-9]{1,4}|(?:[a-fA-F0-9]{1,4}:){1,7}:|(?:[a-fA-F0-9]{1,4}:){1,6}:[a-fA-F0-9]…
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| /openbmc/qemu/tests/tcg/loongarch64/ |
| H A D | test_fcsr.c | 8 "movgr2fr.d $f0,$r0\n\t" in main()
9 "fdiv.d $f0,$f0,$f0\n\t" in main()
11 : "=r"(fcsr) : : "f0"); in main()
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| /openbmc/u-boot/doc/ |
| H A D | README.davinci.nand_spl | 34 00000800 14 00 00 ea 14 f0 9f e5 10 f0 9f e5 0c f0 9f e5 |................|
35 00000810 08 f0 9f e5 04 f0 9f e5 00 f0 9f e5 04 f0 1f e5 |................|
42 00003800 14 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
43 00003810 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
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| H A D | README.chromium | 123 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
126 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
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| /openbmc/bmcweb/test/include/ |
| H A D | ossl_random.cpp | 21 "^[a-f0-9]{8}-[a-f0-9]{4}-[a-f0-9]{4}-[a-f0-9]{4}-[a-f0-9]{12}$")); in TEST()
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| /openbmc/u-boot/arch/x86/include/asm/arch-broadwell/ |
| H A D | serialio.h | 12 #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
15 #define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
25 #define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
39 #define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
46 #define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
50 #define SIO_ID_SDMA 0 /* D21:F0 */
57 #define SIO_ID_SDIO 7 /* D23:F0 */
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| /openbmc/qemu/tests/qtest/ |
| H A D | test-netfilter.c | 23 " 'id': 'qtest-f0'," in add_one_netfilter()
35 " 'id': 'qtest-f0'" in add_one_netfilter()
50 " 'id': 'qtest-f0'," in remove_netdev_with_one_netfilter()
87 " 'id': 'qtest-f0'," in add_multi_netfilter()
112 " 'id': 'qtest-f0'" in add_multi_netfilter()
135 " 'id': 'qtest-f0'," in remove_netdev_with_multi_netfilter()
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| /openbmc/openbmc-test-automation/data/ |
| H A D | pldm_variables.py | 23 VERSION_BASE = {"VALUE": ["f1", "f0", "f0", "00"], "STRING": "1.0.0"}
24 VERSION_PLATFORM = {"VALUE": ["f1", "f2", "f0", "00"], "STRING": "1.2.0"}
26 VERSION_FRU = {"VALUE": ["f1", "f0", "f0", "00"], "STRING": "1.0.0"}
27 VERSION_OEM = {"VALUE": ["f1", "f0", "f0", "00"], "STRING": "1.0.0"}
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | car.S | 57 /* Write MCR B0:D0:F0:RD0 */
65 /* Read MDR B0:D0:F0:RD4 */
88 /* Write MDR B0:D0:F0:RD4 */
96 /* Write MCR B0:D0:F0:RD0 */
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| H A D | quark.c | 70 /* GPIO - D31:F0:R44h */ in quark_setup_bars()
74 /* ACPI PM1 Block - D31:F0:R48h */ in quark_setup_bars()
78 /* GPE0 - D31:F0:R4Ch */ in quark_setup_bars()
82 /* WDT - D31:F0:R84h */ in quark_setup_bars()
86 /* RCBA - D31:F0:RF0h */ in quark_setup_bars()
253 * controller (D23:F0/F1) will not be visible in PCI configuration in arch_cpu_init_dm()
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| /openbmc/bmcweb/test/http/ |
| H A D | utility_test.cpp | 58 encoded = base64encode("f0"); in TEST()
61 encoded = base64encode("f0\0"s); in TEST()
64 encoded = base64encode("f0\0 "s); in TEST()
67 encoded = base64encode("f0\0 B"s); in TEST()
70 encoded = base64encode("f0\0 Ba"s); in TEST()
73 encoded = base64encode("f0\0 Bar"s); in TEST()
80 std::string data = "f0\0 Bar"s; in TEST()
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| /openbmc/qemu/include/hw/southbridge/ |
| H A D | ich9.h | 50 * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
106 /* D29:F0 USB UHCI Controller #1 */
110 /* D30:F0 DMI-to-PCI bridge */
121 /* D31:F0 LPC Processor Interface */
183 /* D31:F0 power management I/O registers
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| /openbmc/u-boot/drivers/pinctrl/mscc/ |
| H A D | mscc-common.h | 35 #define MSCC_P(p, f0, f1, f2) \ argument
39 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
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| /openbmc/u-boot/arch/x86/cpu/queensbay/ |
| H A D | tnc.c | 38 * (D2:F0) from reporting itself as a VGA display controller in disable_igd()
46 * the SDVO (D3:F0) device should be disabled to make it work. in disable_igd()
49 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these in disable_igd()
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| /openbmc/qemu/host/include/loongarch64/host/ |
| H A D | atomic128-ldst.h.inc | 31 : "=r"(l), "=r"(h) : "r"(ptr), "m"(*ptr) : "$f0");
49 : "=m"(*ptr) : "r"(l), "r"(h), "r"(ptr) : "$f0");
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| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
| H A D | UTIL.interface.yaml | 49 - name: F0
52 F0 keyword.
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| H A D | VSBK.interface.yaml | 76 - name: F0
79 F0 keyword.
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | pinmux.c | 257 #define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \ argument
260 PMUX_FUNC_ ## f0, \
270 #define PIN(pingrp, f0, f1, f2, f3) \ argument
271 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
274 #define PINP(pingrp, f0, f1, f2, f3, pupd) \ argument
275 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
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