| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-ntxec.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * e-book readers designed by the original design manufacturer Netronix, Inc.
13 * - The get_state callback is not implemented, because the current state of
15 * - The hardware can only generate normal polarity output.
16 * - The period and duty cycle can't be changed together in one atomic action.
45 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
58 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
63 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
66 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
69 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
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| H A D | pwm-cros-ec.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/mfd/cros_ec.h>
19 * struct cros_ec_pwm_device - Driver data for EC PWM
34 * struct cros_ec_pwm - per-PWM driver data
35 * @duty_cycle: cached duty cycle
52 return -ENOMEM; in cros_ec_pwm_request()
76 return -EINVAL; in cros_ec_dt_type_to_pwm_type()
81 u16 duty) in cros_ec_pwm_set_duty() argument
83 struct cros_ec_device *ec = ec_pwm->ec; in cros_ec_pwm_set_duty()
94 msg->version = 0; in cros_ec_pwm_set_duty()
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| H A D | pwm-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
9 * automatically reloaded at the end of a cycle. If this automatic reload
11 * bad cycle. This could probably be fixed by reading TCR0 just before
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
14 * possible by stopping the counters at an appropriate point in the cycle,
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
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| H A D | pwm-sl28cpld.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
30 * - The duty cycle will switch immediately and not after a complete cycle.
31 * - Depending on the actual implementation, disabling the PWM might have
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| H A D | pwm-iqs620a.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * - The period is fixed to 1 ms and is generated continuously despite changes
9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
13 * ms, the output is disabled and relies upon an external pull-down resistor
46 struct iqs62x_core *iqs62x = iqs620_pwm->iqs62x; in iqs620_pwm_init()
50 return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS, in iqs620_pwm_init()
53 ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE, in iqs620_pwm_init()
54 duty_scale - 1); in iqs620_pwm_init()
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| H A D | pwm-microchip-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
25 * If the duty cycle is 0%, and the requested period is less than the
28 * - The PWM period is set for the whole IP block not per channel. The driver
79 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg in mchp_core_pwm_enable()
82 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
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| H A D | pwm-omap-dmtimer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
20 * - When PWM is stopped, timer counter gets stopped immediately. This
22 * - When PWM is running and changing both duty cycle and period,
27 * - period for current cycle = current_period + new period
28 * - duty_cycle for current period = current period + new duty_cycle.
29 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
31 * - PWM is stopped abruptly(without completing the current cycle)
32 * - Polarity is changed
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| H A D | pwm-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
64 mutex_lock(&ddata->lock); in pwm_sifive_request()
65 ddata->user_count++; in pwm_sifive_request()
66 mutex_unlock(&ddata->lock); in pwm_sifive_request()
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
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| H A D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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| H A D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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| H A D | max31790.rst | 10 Addresses scanned: -
18 -----------
23 PWM outputs. The desired fan speeds (or PWM duty cycles) are written
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
41 fan[1-6]_enable RW enable or disable the tachometer input
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| H A D | f71882fg.rst | 103 This is the 64-pin variant of the F71889FG, they have the
119 -----------
133 ----------
136 interface as documented in sysfs-interface, without any exceptions.
140 -----------
142 Both PWM (pulse-width modulation) and DC fan speed control methods are
149 vica versa. So the temperature zone trip points 1-4 (or 1-2) go from high temp
153 There are 2 modes to specify the speed of the fan, PWM duty cycle (or DC
154 voltage) mode, where 0-100% duty cycle (0-100% of 12V) is specified. And RPM
156 gets specified as 0-100% of the fan#_full_speed file.
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| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | pwm-vibrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
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| /openbmc/u-boot/drivers/pwm/ |
| H A D | Kconfig | 2 bool "Enable support for pulse-width modulation devices (PWM)"
5 A pulse-width modulator emits a pulse of varying width and provides
6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
28 continuous/single-shot) are not supported by the driver.
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
52 programmable period and duty cycle. A 16-bit counter is used.
|
| /openbmc/linux/Documentation/driver-api/thermal/ |
| H A D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
58 ---------------
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
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| /openbmc/linux/include/linux/ |
| H A D | pwm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum pwm_polarity - polarity of a PWM signal
13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
14 * cycle, followed by a low signal for the remainder of the pulse
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
17 * cycle, followed by a high signal for the remainder of the pulse
26 * struct pwm_args - board-dependent PWM arguments
30 * This structure describes board-dependent arguments attached to a PWM
49 * struct pwm_state - state of a PWM channel
51 * @duty_cycle: PWM duty cycle (in nanoseconds)
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| /openbmc/qemu/include/hw/misc/ |
| H A D | npcm7xx_pwm.h | 33 * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
35 * value of 100,000 the duty cycle for that PWM is 10%.
42 * struct NPCM7xxPWM - The state of a single PWM channel.
53 * @duty: The duty cycle of this PWM channel. One unit represents
71 uint32_t duty; member
75 * struct NPCM7xxPWMState - Pulse Width Modulation device state.
80 * @duty_gpio_out: The duty cycle of each PWM channels as a output GPIO.
103 #define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
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| /openbmc/linux/Documentation/devicetree/bindings/leds/backlight/ |
| H A D | pwm-backlight.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight
10 - Lee Jones <lee@kernel.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
16 const: pwm-backlight
21 pwm-names: true
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| /openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/ |
| H A D | ampere_fanctrl.sh | 4 fan_hwmon_num_8_20=$(ls /sys/bus/i2c/drivers/max31790/8-0020/hwmon)
5 fan_hwmon_num_8_2f=$(ls /sys/bus/i2c/drivers/max31790/8-002f/hwmon)
8 phosphor_fan_service=("phosphor-fan-control@0.service"
9 "phosphor-fan-monitor@0.service"
10 "phosphor-fan-presence-tach@0.service")
12 declare -A fan_id_list
31 systemctl daemon-reload
40 systemctl daemon-reload
53 service_stt=$(systemctl is-active "$service" | grep inactive)
54 if [ -n "$service_stt" ]; then
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| /openbmc/linux/Documentation/userspace-api/media/rc/ |
| H A D | lirc-set-send-duty-cycle.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
13 LIRC_SET_SEND_DUTY_CYCLE - Set the duty cycle of the carrier signal for
30 Duty cicle, describing the pulse width in percent (from 1 to 99) of
31 the total cycle. Values 0 and 100 are reserved.
36 Get/set the duty cycle of the carrier signal for IR transmit.
45 On success 0 is returned, on error -1 and the ``errno`` variable is set
47 :ref:`Generic Error Codes <gen-errors>` chapter.
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_panel_cntl.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 dce_panel_cntl->base.ctx
40 dce_panel_cntl->base.ctx->logger
43 dce_panel_cntl->regs->reg
47 dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
68 bl_period_mask = (1 << bl_int_count) - 1; in dce_get_16_bit_backlight_from_pwm()
71 bl_pwm_mask = bl_period_mask << (16 - bl_int_count); in dce_get_16_bit_backlight_from_pwm()
96 * Bios bug w/a - period resets to zero, in dce_panel_cntl_hw_init()
101 if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) { in dce_panel_cntl_hw_init()
103 panel_cntl->stored_backlight_registers.BL_PWM_CNTL); in dce_panel_cntl_hw_init()
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| /openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-utils/ |
| H A D | ampere_fanctrl.sh | 4 fan_hwmon_num=$(ls /sys/bus/i2c/drivers/adt7462/8-005c/hwmon)
7 phosphor_fan_service=("phosphor-fan-control@0.service"
8 "phosphor-fan-monitor@0.service"
9 "phosphor-fan-presence-tach@0.service"
10 "phosphor-pid-control.service")
12 declare -A fan_id_list
24 systemctl daemon-reload
33 systemctl daemon-reload
37 if [ "$service" == "phosphor-pid-control.service" ] &&
38 [ "$(obmcutil chassisstate | awk -F. '{print $NF}')" == 'Off' ]; then
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| /openbmc/linux/sound/pcmcia/pdaudiocf/ |
| H A D | pdaudiocf.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
31 #define PDAUDIOCF_TESTDATASEL (1<<1) /* test data selection, 0 = 0x55, 1 = pseudo-random */
43 #define PDAUDIOCF_DATAFMT0 (1<<10) /* data format bits: 00 = 16-bit, 01 = 18-bit */
44 #define PDAUDIOCF_DATAFMT1 (1<<11) /* 10 = 20-bit, 11 = 24-bit, all right justified */
57 #define PDAUDIOCF_BLUEDUTY0 (1<<8) /* blue LED duty cycle; 00 = 100%, 01 = 50% */
59 #define PDAUDIOCF_REDDUTY0 (1<<10) /* red LED duty cycle; 00 = 100%, 01 = 50% */
62 #define PDAUDIOCF_BLUEMODULATE (1<<13) /* save power when 100% duty cycle selected */
63 #define PDAUDIOCF_REDMODULATE (1<<14) /* save power when 100% duty cycle selected */
108 outw(chip->regmap[reg>>1] = val, chip->port + reg); in pdacf_reg_write()
113 return inw(chip->port + reg); in pdacf_reg_read()
|