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/openbmc/linux/sound/pci/cs46xx/
H A Dcs46xx.h173 * The following defines are for the flags in the host interrupt status
208 * The following defines are for the flags in the host signal register 0.
245 * The following defines are for the flags in the host interrupt control
252 * The following defines are for the flags in the DMA status register.
260 * The following defines are for the flags in the host DMA source address
275 * The following defines are for the flags in the host DMA destination address
290 * The following defines are for the flags in the host DMA control register.
299 * The following defines are for the flags in the host DMA control register.
329 * The following defines are for the flags in the performance monitor control
356 * The following defines are for the flags in the performance counter value 1
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/multipath-tools/files/
H A D0010-Always-use-devmapper.patch29 DEFINES :=
32 - DEFINES += LIBDM_API_FLUSH
36 - DEFINES += LIBDM_API_GET_ERRNO
40 - DEFINES += LIBDM_API_COOKIE
44 - DEFINES += LIBUDEV_API_RECVBUF
48 - DEFINES += LIBDM_API_DEFERRED
52 - DEFINES += LIBDM_API_HOLD_CONTROL
56 - DEFINES += FPIN_EVENT_HANDLER
59 +DEFINES += LIBDM_API_FLUSH
60 +DEFINES += LIBDM_API_GET_ERRNO
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml60 Configure the PD_IDLE value. Defines the power-down idle period in which
69 Configure the SR_IDLE value. Defines the self-refresh idle period in
79 Defines the memory self-refresh and controller clock gating idle period.
89 Defines the self-refresh power down idle period in which memories are
99 Defines the standby idle period in which memories are placed into
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
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H A Dst,stm32-fmc2-ebi-props.yaml89 description: This property defines the duration of the address setup
93 description: This property defines the duration of the address hold
98 description: This property defines the duration of the data setup phase
102 description: This property defines the delay in nanoseconds between the
106 description: This property defines the duration of the data hold phase
110 description: This property defines the FMC_CLK output signal period in
114 description: This property defines the data latency before reading or
118 description: This property defines the duration of the address setup
122 description: This property defines the duration of the address hold
127 description: This property defines the duration of the data setup
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H A Dmvebu-devbus.txt37 - devbus,turn-off-ps: Defines the time during which the controller does not
43 - devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
52 - devbus,acc-first-ps: Defines the time delay from the negation of
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
62 - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
71 - devbus,rd-hold-ps: Defines the time between the last data sample to the
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
89 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
91 is active. This parameter defines the setup time of
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/openbmc/u-boot/doc/
H A DREADME.m68k98 To specify a CPU model, some defines shoudl be used, i.e.:
106 CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration
109 -- defines the base address of the FEC buffer descriptors
110 CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
111 CONFIG_SYS_SPR -- defines the contents of the System Protection Register
112 CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Divider
114 CONFIG_SYS_RFD -- defines the PLL Reduce Frequency Devider
117 -- defines the base address of chip select x
119 -- defines the memory size (address range) of chip select x
121 -- defines the bus with of chip select x
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H A DREADME.bus_vcxk24 The driver needs some defines to describe the target hardware:
32 defines the physical alignment of a pixel row
41 defines the number of the I/O line PIN in the port
61 defines the I/O port which is connected with the line
66 defines the register which configures the direction
/openbmc/linux/include/uapi/drm/
H A Dqaic_accel.h56 * @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
65 * struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
76 * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
93 * struct qaic_manage_trans_activate_to_dev - Defines an activate request.
109 * struct qaic_manage_trans_activate_from_dev - Defines an activate response.
123 * struct qaic_manage_trans_deactivate - Defines a deactivate request.
135 * struct qaic_manage_trans_status_to_dev - Defines a status request.
143 * struct qaic_manage_trans_status_from_dev - Defines a status response.
159 * struct qaic_manage_msg - Defines a message to the device.
171 * struct qaic_create_bo - Defines a request to create a buffer object.
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/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_history.txt52 * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and
54 * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines.
64 * 03-14-02 01.02.04 Added MPI_HEADER_VERSION_ defines.
79 * 08-19-04 01.05.01 Added defines for Host Buffer Access Control doorbell.
121 * 01-09-01 01.01.03 Added event enabled and disabled defines.
127 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER.
134 * related structure and defines.
142 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field.
147 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_.
148 * 06-26-03 01.02.08 Added new values to the product family defines.
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/openbmc/linux/drivers/edac/
H A Daltera_edac.h41 /* SDRAM Controller Interface Data Width Defines */
111 /* SDRAM Controller Interface Data Width Defines */
190 /************************** EDAC Device Defines **************************/
191 /***** General Device Trigger Defines *****/
197 /******* Cyclone5 and Arria5 Defines *******/
198 /* OCRAM ECC Management Group Defines */
207 /* L2 ECC Management Group Defines */
214 /* Arria10 General ECC Block Module Defines */
248 /* ECC Manager Defines */
262 /* Arria 10 L2 ECC Management Group Defines */
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/openbmc/linux/drivers/scsi/mpt3sas/mpi/
H A Dmpi2_raid.h28 * related structures and defines.
52 /* ActionDataWord defines for use with MPI2_RAID_ACTION_CREATE_VOLUME action */
55 /*ActionDataWord defines for use with MPI2_RAID_ACTION_DELETE_VOLUME action */
59 /*use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for
62 /*ActionDataWord defines for use with
88 /*defines for the RAIDFunction field */
93 /*defines for the Flags field */
107 /*defines for the RAIDFunction field */
112 /*defines for the Flags field */
134 /*ActionDataWord defines for use with
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H A Dmpi2_cnfg.h12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
72 * Added additional defines for RAID Volume Page 0
77 * added related defines.
78 * Added PhysDiskAttributes field (and related defines) to
90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
94 * VolumeStatusFlags defines.
99 * Removed SATA Init Failure defines for DiscoveryStatus
104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
114 * Added PhyInfo defines for power condition.
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/openbmc/linux/drivers/net/ipa/
H A Dipa_qmi_msg.h89 /* This defines the start and end offset of a range of memory. The start
100 /* This defines the location and size of an array. The start value
110 /* This defines the location and size of a range of memory. The
128 /* Modem header table information. This defines the IPA shared
153 /* Modem memory information. This defines the location and
159 /* This defines the destination endpoint on the AP to which
166 /* This defines whether the modem should load the microcontroller
175 /* Processing context memory information. This defines the memory in
181 /* Compression command memory information. This defines the memory
228 /* This defines the destination endpoint on the modem to which
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Telemetry/
H A DTrigger.interface.yaml17 Defines actions which are taken when threshold conditions are met.
22 description: Defines if Trigger is stored in non volatile memory.
52 Defines the name of trigger to be exposed over D-Bus.
57 Defines a action which is taken once threshold condition is met.
69 Defines a context of a message that is logged when numeric threshold
78 Defines in which direction threshold value is crossed to fulfill
95 Defines a context of a message that is logged when discrete threshold
H A DReport.interface.yaml32 Defines if the report configuration is stored in non volatile memory.
57 description: Defines how readings are updated.
62 description: Defines how Readings array is filled.
65 description: Defines the maximum number of entries in 'Readings' property.
71 Defines period of time in milliseconds when readings are updated.
84 Defines the name of reading report to be exposed over D-Bus.
117 The type that defines when Readings are updated.
130 The type that defines how Readings are updated.
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-dbs/mongodb/mongodb/
H A Darm64-support.patch22 'arm' : { 'endian': 'little', 'defines': ('__arm__',) },
23 'aarch64' : { 'endian': 'little', 'defines': ('__arm64__', '__aarch64__')},
24 + 'arm64' : { 'endian': 'little', 'defines': ('__arm64__', '__aarch64__')},
25 'i386' : { 'endian': 'little', 'defines': ('__i386', '_M_IX86')},
26 'ppc64le' : { 'endian': 'little', 'defines': ('__powerpc64__',)},
27 's390x' : { 'endian': 'big', 'defines': ('__s390x__',)},
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/pad/
H A Dapi.h9 /* Defines for sc_pad_config_t */
15 /* Defines for sc_pad_iso_t */
21 /* Defines for sc_pad_28fdsoi_dse_t */
37 /* Defines for sc_pad_28fdsoi_ps_t */
43 /* Defines for sc_pad_28fdsoi_pus_t */
49 /* Defines for sc_pad_wakeup_t */
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/misc/
H A Dapi.h9 /* Defines for sc_misc_boot_status_t */
13 /* Defines for sc_misc_seco_auth_cmd_t */
18 /* Defines for sc_misc_temp_t */
23 /* Defines for sc_misc_seco_auth_cmd_t */
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.h13 /* System Memory Controller Register Defines */
45 /* DRP register defines */
53 /* DTR0 register defines */
59 /* DTR1 register defines */
71 /* DTR2 register defines */
76 /* DTR3 register defines */
83 /* DTR4 register defines */
91 /* DPMC0 register defines */
99 /* DRFC register defines */
103 /* DSCH register defines */
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100.h18 * MAC BLOCK defines
32 /* MAC CTRL defines */
61 /* MAC FLOW CTRL defines */
68 /* MII ADDR defines */
73 * DMA BLOCK defines
76 /* DMA Bus Mode register defines */
86 /* DMA Control register defines */
103 /* STMAC110 DMA Missed Frame Counter register defines */
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Dgpi.h42 /* GPI commons defines */
46 /* EGPI 1 defines */
51 /* EGPI 2 defines */
56 /* HGPI defines */
/openbmc/u-boot/board/keymile/scripts/
H A DREADME14 This file defines variables for working with rootfs via nfs for powerpc and
19 This file defines architecture specific variables for working with rootfs via
25 This file defines variables for working with rootfs inside the ram for powerpc
30 This file defines architecture specific variables for working with rootfs inside
/openbmc/linux/drivers/net/pcs/
H A Dpcs-xpcs.h42 /* Clause 73 Defines */
55 /* Clause 37 Defines */
98 /* SR MII MMD Control defines */
103 /* SR MII MMD AN Advertisement defines */
107 /* VR MII EEE Control 0 defines */
118 /* VR MII EEE Control 1 defines */
/openbmc/u-boot/Documentation/sphinx/
H A Dparse-headers.pl25 my %defines;
84 $defines{$s} = "\\ :ref:`$s <$n>`\\ ";
157 delete $defines{$1} if (exists($defines{$1}));
204 $defines{$old} = $new if (exists($defines{$old}));
233 print Data::Dumper->Dump([\%defines], [qw(*defines)]) if (%defines);
270 foreach my $r (keys %defines) {
271 my $s = $defines{$r};
341 enums and defines and create cross-references to a Sphinx book.
377 It is capable of identifying defines, functions, structs, typedefs,
/openbmc/linux/Documentation/sphinx/
H A Dparse-headers.pl25 my %defines;
84 $defines{$s} = "\\ :ref:`$s <$n>`\\ ";
157 delete $defines{$1} if (exists($defines{$1}));
204 $defines{$old} = $new if (exists($defines{$old}));
233 print Data::Dumper->Dump([\%defines], [qw(*defines)]) if (%defines);
270 foreach my $r (keys %defines) {
271 my $s = $defines{$r};
341 enums and defines and create cross-references to a Sphinx book.
377 It is capable of identifying defines, functions, structs, typedefs,

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