| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dsb.c | 45 * ins_start_offset will help to store start dword of the dsb
53 * DOC: DSB
55 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
56 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
57 * engine that can be programmed to download the DSB from memory.
60 * faster. DSB Support added from Gen12 Intel graphics based platform.
62 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
65 * DSB HW can support only register writes (both indexed and direct MMIO
66 * writes). There are no registers reads possible with DSB HW engine.
69 /* DSB opcodes. */
[all …]
|
| H A D | intel_dsb.h | 18 void intel_dsb_finish(struct intel_dsb *dsb);
19 void intel_dsb_cleanup(struct intel_dsb *dsb);
20 void intel_dsb_reg_write(struct intel_dsb *dsb,
22 void intel_dsb_commit(struct intel_dsb *dsb,
24 void intel_dsb_wait(struct intel_dsb *dsb);
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
14 "PublicDescription": "Number of DSB to MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
22 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
27 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
30 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
63 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
72 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
14 "PublicDescription": "Number of DSB to MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
22 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
27 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
30 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
63 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
72 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /openbmc/linux/arch/arm64/kvm/hyp/vhe/ |
| H A D | tlb.c | 87 dsb(ishst); in __kvm_tlb_flush_vmid_ipa()
106 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
108 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
119 dsb(nshst); in __kvm_tlb_flush_vmid_ipa_nsh()
138 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
140 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
159 dsb(ishst); in __kvm_tlb_flush_vmid_range()
166 dsb(ish); in __kvm_tlb_flush_vmid_range()
168 dsb(ish); in __kvm_tlb_flush_vmid_range()
178 dsb(ishst); in __kvm_tlb_flush_vmid()
[all …]
|
| /openbmc/linux/fs/erofs/ |
| H A D | super.c | 54 struct erofs_super_block *dsb; in erofs_superblock_csum_verify() local
60 dsb = kmemdup(sbdata + EROFS_SUPER_OFFSET, len, GFP_KERNEL); in erofs_superblock_csum_verify()
61 if (!dsb) in erofs_superblock_csum_verify()
64 expected_crc = le32_to_cpu(dsb->checksum); in erofs_superblock_csum_verify()
65 dsb->checksum = 0; in erofs_superblock_csum_verify()
67 crc = crc32c(~0, dsb, len); in erofs_superblock_csum_verify()
68 kfree(dsb); in erofs_superblock_csum_verify()
109 struct erofs_super_block *dsb) in check_layout_compatibility() argument
111 const unsigned int feature = le32_to_cpu(dsb->feature_incompat); in check_layout_compatibility()
161 struct erofs_super_block *dsb) in z_erofs_parse_cfgs() argument
[all …]
|
| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | tlbflush.h | 35 "dsb ish\n tlbi " #op, \
43 "dsb ish\n tlbi " #op ", %0", \
177 * DSB ISHST // Ensure prior page-table updates have completed
179 * DSB ISH // Ensure the TLB invalidation has completed
239 dsb(nshst); in local_flush_tlb_all()
241 dsb(nsh); in local_flush_tlb_all()
247 dsb(ishst); in flush_tlb_all()
249 dsb(ish); in flush_tlb_all()
257 dsb(ishst); in flush_tlb_mm()
261 dsb(ish); in flush_tlb_mm()
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
39 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
101 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | tlb.c | 25 * CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN in __tlb_switch_to_guest()
31 * registers out of context, for which dsb(nsh) is enough in __tlb_switch_to_guest()
33 * The composition of these two barriers is a dsb(DOMAIN), and in __tlb_switch_to_guest()
39 dsb(nsh); in __tlb_switch_to_guest()
41 dsb(ish); in __tlb_switch_to_guest()
103 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
105 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
155 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
157 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
203 dsb(ish); in __kvm_tlb_flush_vmid_range()
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
39 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
101 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
51 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
60 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
83 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
94 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = …
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
149 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
51 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
60 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
83 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
94 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = …
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
149 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | frontend.json | 26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
29 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
34 "BriefDescription": "Retired Instructions who experienced DSB miss.",
40 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
45 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
51 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
257 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
261 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
266 "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
270 …line) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
[all …]
|
| /openbmc/linux/arch/arm/include/asm/ |
| H A D | barrier.h | 20 #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") macro
31 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
38 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
43 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
58 #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
60 #define __arm_heavy_mb(x...) dsb(x)
65 #define rmb() dsb()
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | barriers.h | 34 #define DSB asm volatile ("dsb sy" : : : "memory") macro
38 #define DSB CP15DSB macro
42 #define DSB CP15DSB macro
47 #define dsb() DSB macro
|