Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:r5f (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx R5F processor subsystem
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
[all …]
H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zcu102.rst1 Xilinx ZynqMP ZCU102 (``xlnx-zcu102``)
4 The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board.
5 This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs.
7 Machine-specific options
10 The following machine-specific options are supported:
H A Demulation.rst3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
21 interrupt-parent = <&gic500>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 #address-cells = <1>;
[all …]
H A Dk3-j7200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12 #include "k3-pinctrl.h"
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
H A Dk3-j784s4.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
20 interrupt-parent = <&gic500>;
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
[all …]
H A Dk3-j721e.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/soc/ti,sci_pm_domain.h>
12 #include "k3-pinctrl.h"
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 #address-cells = <1>;
[all …]
H A Dk3-am65.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
13 #include "k3-pinctrl.h"
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
H A Dk3-am62-verdin.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/net/ti-dp83867.h>
18 stdout-path = "serial2:115200n8";
45 verdin_gpio_keys: gpio-keys {
46 compatible = "gpio-keys";
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 * reflects possible values of xlnx,cluster-mode dt-property
34 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
39 * struct mem_bank_data - Memory Bank description
43 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
76 * accepted for system-dt specifications and upstreamed in linux kernel
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/openbmc/u-boot/board/ti/am65x/
H A DREADME2 -------------
9 1. Wake-up (WKUP) domain:
10 - Device Management and Security Controller (DMSC)
12 - Dual Core ARM Cortex-R5F processor
14 - Quad core 64-bit ARM Cortex-A53
19 ----------
27 2. U-Boot on A53 should start other remotecores for various
29 3. In production boot flow, we might not like to use full u-boot,
32 +------------------------------------------------------------------------+
34 +------------------------------------------------------------------------+
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/
H A D0001-remoteproc-Add-Arm-remoteproc-driver.patch12 The current use case is Corstone-1000 External System (Cortex-M3).
20 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
21 Upstream-Status: Denied [Agreement reached: https://lore.kernel.org/all/20241009094635.GA14639@e130…
22 ---
30 diff --git a/MAINTAINERS b/MAINTAINERS
32 --- a/MAINTAINERS
34 @@ -1764,6 +1764,12 @@ S: Maintained
35 F: Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml
36 F: drivers/irqchip/irq-vic.c
40 +L: linux-remoteproc@vger.kernel.org
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
28 t = cpu->isar.id_isar5; in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c21 #include "hw/arm/xlnx-zynqmp.h"
28 #include "target/arm/cpu-qom.h"
218 int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), in xlnx_zynqmp_create_rpu()
222 /* Don't create rpu-cluster object if there's nothing to put in it */ in xlnx_zynqmp_create_rpu()
226 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, in xlnx_zynqmp_create_rpu()
228 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); in xlnx_zynqmp_create_rpu()
233 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", in xlnx_zynqmp_create_rpu()
234 &s->rpu_cpu[i], in xlnx_zynqmp_create_rpu()
235 ARM_CPU_TYPE_NAME("cortex-r5f")); in xlnx_zynqmp_create_rpu()
237 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); in xlnx_zynqmp_create_rpu()
[all …]
H A Dxlnx-versal.c24 #include "hw/arm/xlnx-versal.h"
26 #include "target/arm/cpu-qom.h"
29 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
30 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
40 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, in versal_create_apu_cpus()
42 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); in versal_create_apu_cpus()
44 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { in versal_create_apu_cpus()
47 object_initialize_child(OBJECT(&s->fpd.apu.cluster), in versal_create_apu_cpus()
48 "apu-cpu[*]", &s->fpd.apu.cpu[i], in versal_create_apu_cpus()
50 obj = OBJECT(&s->fpd.apu.cpu[i]); in versal_create_apu_cpus()
[all …]
/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
[all...]