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/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa32.inc3 TUNEVALID[cortexa32] = "Enable Cortex-A32 specific processor optimizations"
4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa32', ' -mcpu=cortex-a32', '', d)}"
6 require conf/machine/include/arm/arch-armv8a.inc
9 AVAILTUNES += "cortexa32 cortexa32-crypto"
10 ARMPKGARCH:tune-cortexa32 = "cortexa32"
11 ARMPKGARCH:tune-cortexa32-crypto = "cortexa32"
12 # We do not want -march since -mcpu is added above to cover for it
13 TUNE_FEATURES:tune-cortexa32 = "armv8a cortexa32 crc callconvention-hard neon"
14 TUNE_FEATURES:tune-cortexa32-crypto = "${TUNE_FEATURES:tune-cortexa32} crypto"
15 PACKAGE_EXTRA_ARCHS:tune-cortexa32 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa32 …
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
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H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/openbmc/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
260 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
301 # VA_BITS - PAGE_SHIFT - 3
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
432 at stage-2.
440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
454 data cache clean-and-invalidate.
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/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c5 * Copyright (c) 2005-2007 CodeSourcery
24 #include "translate-a32.h"
29 #include "exec/helper-proto.h"
32 #include "exec/helper-info.c.inc"
87 /* no-op */ in asimd_imm_const()
155 if (!s->condjmp) { in arm_gen_condlabel()
156 s->condlabel = gen_disas_label(s); in arm_gen_condlabel()
157 s->condjmp = 1; in arm_gen_condlabel()
224 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store" in get_a32_user_mem_index()
229 switch (s->mmu_idx) { in get_a32_user_mem_index()
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/openbmc/qemu/target/arm/
H A Dcpu.h23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
79 /* ARM-specific interrupt pending bits. */
102 /* ARM-specific extra insn start words:
113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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